On Mon, 2 Mar 2026, Chad Jablonski wrote:
> Writing to any of the HOST_DATA0-7 registers pushes the written data
> into a 128-bit accumulator. When the accumulator is full a flush is
> triggered to copy it to the framebuffer. A final write to HOST_DATA_LAST
> will also initiate a flush. The flush itself is left for the next patch.
>
> Unaligned HOST_DATA* writes result in, from what I can tell, undefined
> behavior on real hardware. A well-behaved driver shouldn't be doing this
> anyway. For that reason they are not handled here at all.
>
> Signed-off-by: Chad Jablonski <chad@jablonski.xyz>
Reviewed-by: BALATON Zoltan <balaton@eik.bme.hu>
> ---
> hw/display/ati.c | 26 ++++++++++++++++++++++++++
> hw/display/ati_dbg.c | 9 +++++++++
> hw/display/ati_int.h | 9 +++++++++
> hw/display/ati_regs.h | 9 +++++++++
> 4 files changed, 53 insertions(+)
>
> diff --git a/hw/display/ati.c b/hw/display/ati.c
> index 6cf243bcf9..fa31401ba6 100644
> --- a/hw/display/ati.c
> +++ b/hw/display/ati.c
> @@ -1024,6 +1024,27 @@ static void ati_mm_write(void *opaque, hwaddr addr,
> case SRC_SC_BOTTOM:
> s->regs.src_sc_bottom = data & 0x3fff;
> break;
> + case HOST_DATA0:
> + case HOST_DATA1:
> + case HOST_DATA2:
> + case HOST_DATA3:
> + case HOST_DATA4:
> + case HOST_DATA5:
> + case HOST_DATA6:
> + case HOST_DATA7:
> + case HOST_DATA_LAST:
> + if (!s->host_data.active) {
> + break;
> + }
> + s->host_data.acc[s->host_data.next++] = data;
> + if (addr == HOST_DATA_LAST) {
> + qemu_log_mask(LOG_UNIMP, "HOST_DATA finish not yet implemented\n");
> + s->host_data.next = 0;
> + } else if (s->host_data.next >= 4) {
> + qemu_log_mask(LOG_UNIMP, "HOST_DATA flush not yet implemented\n");
> + s->host_data.next = 0;
> + }
> + break;
> default:
> break;
> }
> @@ -1129,6 +1150,11 @@ static void ati_vga_reset(DeviceState *dev)
> /* reset vga */
> vga_common_reset(&s->vga);
> s->mode = VGA_MODE;
> +
> + s->host_data.active = false;
> + s->host_data.next = 0;
> + s->host_data.row = 0;
> + s->host_data.col = 0;
> }
>
> static void ati_vga_exit(PCIDevice *dev)
> diff --git a/hw/display/ati_dbg.c b/hw/display/ati_dbg.c
> index 3ffa7f35df..5c799d540a 100644
> --- a/hw/display/ati_dbg.c
> +++ b/hw/display/ati_dbg.c
> @@ -252,6 +252,15 @@ static struct ati_regdesc ati_reg_names[] = {
> {"MC_SRC1_CNTL", 0x19D8},
> {"TEX_CNTL", 0x1800},
> {"RAGE128_MPP_TB_CONFIG", 0x01c0},
> + {"HOST_DATA0", 0x17c0},
> + {"HOST_DATA1", 0x17c4},
> + {"HOST_DATA2", 0x17c8},
> + {"HOST_DATA3", 0x17cc},
> + {"HOST_DATA4", 0x17d0},
> + {"HOST_DATA5", 0x17d4},
> + {"HOST_DATA6", 0x17d8},
> + {"HOST_DATA7", 0x17dc},
> + {"HOST_DATA_LAST", 0x17e0},
> {NULL, -1}
> };
>
> diff --git a/hw/display/ati_int.h b/hw/display/ati_int.h
> index 98f57ca5fa..baa264215c 100644
> --- a/hw/display/ati_int.h
> +++ b/hw/display/ati_int.h
> @@ -95,6 +95,14 @@ typedef struct ATIVGARegs {
> uint32_t default_tile;
> } ATIVGARegs;
>
> +typedef struct ATIHostDataState {
> + bool active;
> + uint32_t row;
> + uint32_t col;
> + uint32_t next;
> + uint32_t acc[4];
> +} ATIHostDataState;
> +
> struct ATIVGAState {
> PCIDevice dev;
> VGACommonState vga;
> @@ -112,6 +120,7 @@ struct ATIVGAState {
> MemoryRegion io;
> MemoryRegion mm;
> ATIVGARegs regs;
> + ATIHostDataState host_data;
> };
>
> const char *ati_reg_name(int num);
> diff --git a/hw/display/ati_regs.h b/hw/display/ati_regs.h
> index 3999edb9b7..48f15e9b1d 100644
> --- a/hw/display/ati_regs.h
> +++ b/hw/display/ati_regs.h
> @@ -252,6 +252,15 @@
> #define DP_T12_CNTL 0x178c
> #define DST_BRES_T1_LNTH 0x1790
> #define DST_BRES_T2_LNTH 0x1794
> +#define HOST_DATA0 0x17c0
> +#define HOST_DATA1 0x17c4
> +#define HOST_DATA2 0x17c8
> +#define HOST_DATA3 0x17cc
> +#define HOST_DATA4 0x17d0
> +#define HOST_DATA5 0x17d4
> +#define HOST_DATA6 0x17d8
> +#define HOST_DATA7 0x17dc
> +#define HOST_DATA_LAST 0x17e0
> #define SCALE_SRC_HEIGHT_WIDTH 0x1994
> #define SCALE_OFFSET_0 0x1998
> #define SCALE_PITCH 0x199c
>