Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/i386/tcg/decode-new.h     | 3 +++
 target/i386/tcg/decode-new.c.inc | 4 ++++
 target/i386/tcg/emit.c.inc       | 2 ++
 3 files changed, 9 insertions(+)

diff --git a/target/i386/tcg/decode-new.h b/target/i386/tcg/decode-new.h
index 4998712e86d..8650b5ae7a0 100644
--- a/target/i386/tcg/decode-new.h
+++ b/target/i386/tcg/decode-new.h
@@ -212,6 +212,9 @@ typedef enum X86InsnSpecial {
      */
     X86_SPECIAL_Op0_Rd,
 
+    /* ZU-modified APX instruction.  */
+    X86_SPECIAL_Op0_ZU,
+
     /*
      * Ry/Mb in the manual (PINSRB).  However, the high bits are never used by
      * the instruction in either the register or memory cases; the *real* effect
diff --git a/target/i386/tcg/decode-new.c.inc b/target/i386/tcg/decode-new.c.inc
index c14a07be5ff..adb5595ddf3 100644
--- a/target/i386/tcg/decode-new.c.inc
+++ b/target/i386/tcg/decode-new.c.inc
@@ -3228,6 +3228,10 @@ static void disas_insn(DisasContext *s, CPUState *cpu)
         accept_lock = decode.op[0].has_ea;
         break;
 
+    case X86_SPECIAL_Op0_ZU:
+        assert(decode.op[0].unit == X86_OP_INT);
+        break;
+
     case X86_SPECIAL_Op0_Rd:
         assert(decode.op[0].unit == X86_OP_INT);
         if (!decode.op[0].has_ea) {
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index ce636b6c56c..94a2bb49172 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -347,6 +347,8 @@ static void gen_writeback(DisasContext *s, X86DecodedInsn *decode, int opn, TCGv
     case X86_OP_INT:
         if (op->has_ea) {
             gen_op_st_v(s, op->ot, v, s->A0);
+        } else if (decode->e.special == X86_SPECIAL_Op0_ZU) {
+            tcg_gen_ext_tl(cpu_regs[op->n], v, op->ot);
         } else {
             gen_op_mov_reg_v(s, op->ot, op->n, v);
         }
-- 
2.52.0