On 27/2/26 21:36, Brian Cain wrote:
> From: Brian Cain <bcain@quicinc.com>
>
> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
> ---
> target/hexagon/translate.h | 5 +++++
> target/hexagon/translate.c | 16 ++++++++++++++++
> 2 files changed, 21 insertions(+)
>
> diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
> index 2804e08ce57..f80830f5f16 100644
> --- a/target/hexagon/translate.h
> +++ b/target/hexagon/translate.h
> @@ -281,6 +281,11 @@ extern TCGv_i64 hex_llsc_val_i64;
> extern TCGv hex_vstore_addr[VSTORES_MAX];
> extern TCGv hex_vstore_size[VSTORES_MAX];
> extern TCGv hex_vstore_pending[VSTORES_MAX];
> +#ifndef CONFIG_USER_ONLY
> +extern TCGv hex_greg[NUM_GREGS];
> +extern TCGv hex_t_sreg[NUM_SREGS];
Hexagon has 32-bit registers, so please use TCGv_i32 ...
> +#endif
> +
>
> void hex_gen_exception_end_tb(DisasContext *ctx, int excp);
>
> diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
> index f44080608b5..f3dc62cec1d 100644
> --- a/target/hexagon/translate.c
> +++ b/target/hexagon/translate.c
> @@ -66,6 +66,8 @@ TCGv hex_vstore_size[VSTORES_MAX];
> TCGv hex_vstore_pending[VSTORES_MAX];
>
> #ifndef CONFIG_USER_ONLY
> +TCGv hex_greg[NUM_GREGS];
> +TCGv hex_t_sreg[NUM_SREGS];
> TCGv hex_cause_code;
> #endif
>
> @@ -1099,6 +1101,20 @@ void hexagon_translate_init(void)
>
> opcode_init();
>
> +#ifndef CONFIG_USER_ONLY
> + for (i = 0; i < NUM_GREGS; i++) {
> + hex_greg[i] = tcg_global_mem_new(tcg_env,
... and tcg_global_mem_new_i32().
> + offsetof(CPUHexagonState, greg[i]),
> + hexagon_gregnames[i]);
> + }
> + for (i = 0; i < NUM_SREGS; i++) {
> + if (i < HEX_SREG_GLB_START) {
> + hex_t_sreg[i] = tcg_global_mem_new(tcg_env,
> + offsetof(CPUHexagonState, t_sreg[i]),
> + hexagon_sregnames[i]);
> + }
> + }
> +#endif
> for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) {
> hex_gpr[i] = tcg_global_mem_new(tcg_env,
> offsetof(CPUHexagonState, gpr[i]),