Hexagon system emulation - Part 1/3

[PATCH v3 10/37] target/hexagon: Add memory order definition

Posted by Brian Cain 2 days, 12 hours ago

From: Brian Cain <bcain@quicinc.com>

Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
---
 target/hexagon/cpu-param.h | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h
index 45ee7b46409..ccaf6a9d28d 100644
--- a/target/hexagon/cpu-param.h
+++ b/target/hexagon/cpu-param.h
@@ -23,4 +23,9 @@
 #define TARGET_PHYS_ADDR_SPACE_BITS 36
 #define TARGET_VIRT_ADDR_SPACE_BITS 32
 
+/*
+ * Hexagon processors have a strong memory model.
+ */
+#define TCG_GUEST_DEFAULT_MO      (TCG_MO_ALL)
+
 #endif
-- 
2.34.1

Re: [PATCH v3 10/37] target/hexagon: Add memory order definition

Posted by Philippe Mathieu-Daudé 2 days, 10 hours ago

On 27/2/26 21:36, Brian Cain wrote:
> From: Brian Cain <bcain@quicinc.com>
> 
> Signed-off-by: Brian Cain <brian.cain@oss.qualcomm.com>
> ---
>   target/hexagon/cpu-param.h | 5 +++++
>   1 file changed, 5 insertions(+)
> 
> diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h
> index 45ee7b46409..ccaf6a9d28d 100644
> --- a/target/hexagon/cpu-param.h
> +++ b/target/hexagon/cpu-param.h
> @@ -23,4 +23,9 @@
>   #define TARGET_PHYS_ADDR_SPACE_BITS 36
>   #define TARGET_VIRT_ADDR_SPACE_BITS 32
>   
> +/*
> + * Hexagon processors have a strong memory model.
> + */
> +#define TCG_GUEST_DEFAULT_MO      (TCG_MO_ALL)

This definition is poisoned since commit 98c7c146988.

Commit 7dc2af9786e ("tcg: Remove the TCG_GUEST_DEFAULT_MO
definition globally") already sets
hexagon_tcg_ops::guest_default_memory_order = TCG_MO_ALL.

Maybe just drop this patch?