During MPIPL (aka fadump), after a kernel crash, the kernel does
opal_cec_reboot2 opal call, signifying an abnormal termination.
When OPAL recieves this opal call, it further triggers SBE S0 interrupt,
to trigger a MPIPL boot.
Currently S0 interrupt is unimplemented in QEMU.
Implement S0 interrupt as 'pause_vcpus' + 'guest_reset' in QEMU, as the
SBE's implementation of S0 seems to be basically "stop all clocks" and
then "host reset".
pause_vcpus is done in a later patch when register preserving support is
added
See 'stopClocksS0' in SBE source code for more information.
Also log both S0 and S1 interrupts.
Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
---
hw/ppc/meson.build | 1 +
hw/ppc/pnv_mpipl.c | 26 ++++++++++++++++++++++++++
hw/ppc/pnv_sbe.c | 29 +++++++++++++++++++++++++++++
include/hw/ppc/pnv.h | 6 ++++++
include/hw/ppc/pnv_mpipl.h | 19 +++++++++++++++++++
5 files changed, 81 insertions(+)
create mode 100644 hw/ppc/pnv_mpipl.c
create mode 100644 include/hw/ppc/pnv_mpipl.h
diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
index f7dac87a2a48..c61fba4ec8f2 100644
--- a/hw/ppc/meson.build
+++ b/hw/ppc/meson.build
@@ -56,6 +56,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files(
'pnv_pnor.c',
'pnv_nest_pervasive.c',
'pnv_n1_chiplet.c',
+ 'pnv_mpipl.c',
))
# PowerPC 4xx boards
ppc_ss.add(when: 'CONFIG_PPC405', if_true: files(
diff --git a/hw/ppc/pnv_mpipl.c b/hw/ppc/pnv_mpipl.c
new file mode 100644
index 000000000000..d8c9b7a428b7
--- /dev/null
+++ b/hw/ppc/pnv_mpipl.c
@@ -0,0 +1,26 @@
+/*
+ * Emulation of MPIPL (Memory Preserving Initial Program Load), aka fadump
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#include "qemu/osdep.h"
+#include "system/runstate.h"
+#include "hw/ppc/pnv.h"
+#include "hw/ppc/pnv_mpipl.h"
+
+void do_mpipl_preserve(PnvMachineState *pnv)
+{
+ /* Mark next boot as Memory-preserving boot */
+ pnv->mpipl_state.is_next_boot_mpipl = true;
+
+ /*
+ * Do a guest reset.
+ * Next reset will see 'is_next_boot_mpipl' as true, and trigger MPIPL
+ *
+ * Requirement:
+ * GUEST_RESET is expected to NOT clear the memory, as is the case when
+ * this is merged
+ */
+ qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
+}
diff --git a/hw/ppc/pnv_sbe.c b/hw/ppc/pnv_sbe.c
index 247617338a0d..5a2b3342d199 100644
--- a/hw/ppc/pnv_sbe.c
+++ b/hw/ppc/pnv_sbe.c
@@ -26,6 +26,9 @@
#include "hw/ppc/pnv.h"
#include "hw/ppc/pnv_xscom.h"
#include "hw/ppc/pnv_sbe.h"
+#include "hw/ppc/pnv_mpipl.h"
+#include "system/cpus.h"
+#include "system/runstate.h"
#include "trace.h"
/*
@@ -113,11 +116,37 @@ static uint64_t pnv_sbe_power9_xscom_ctrl_read(void *opaque, hwaddr addr,
static void pnv_sbe_power9_xscom_ctrl_write(void *opaque, hwaddr addr,
uint64_t val, unsigned size)
{
+ PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
+ PnvSBE *sbe = opaque;
uint32_t offset = addr >> 3;
trace_pnv_sbe_xscom_ctrl_write(addr, val);
switch (offset) {
+ case SBE_CONTROL_REG_RW:
+ switch (val) {
+ case SBE_CONTROL_REG_S0:
+ qemu_log_mask(LOG_UNIMP, "SBE: S0 Interrupt triggered\n");
+
+ pnv_sbe_set_host_doorbell(sbe, sbe->host_doorbell | SBE_HOST_RESPONSE_MASK);
+
+ /* Preserve memory regions and CPU state, if MPIPL is registered */
+ do_mpipl_preserve(pnv);
+
+ /*
+ * Control may not come back here as 'do_mpipl_preserve' triggers
+ * a guest reboot
+ */
+ break;
+ case SBE_CONTROL_REG_S1:
+ qemu_log_mask(LOG_UNIMP, "SBE: S1 Interrupt triggered\n");
+ break;
+ default:
+ qemu_log_mask(LOG_UNIMP,
+ "SBE: CONTROL_REG_RW: Unknown value: Ox%."
+ HWADDR_PRIx "\n", val);
+ }
+ break;
default:
qemu_log_mask(LOG_UNIMP, "SBE Unimplemented register: Ox%"
HWADDR_PRIx "\n", addr >> 3);
diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
index 24f8843a4090..7d73629f112a 100644
--- a/include/hw/ppc/pnv.h
+++ b/include/hw/ppc/pnv.h
@@ -25,6 +25,7 @@
#include "hw/core/sysbus.h"
#include "hw/ipmi/ipmi.h"
#include "hw/ppc/pnv_pnor.h"
+#include "hw/ppc/pnv_mpipl.h"
#define TYPE_PNV_CHIP "pnv-chip"
@@ -111,6 +112,8 @@ struct PnvMachineState {
bool big_core;
bool lpar_per_core;
+
+ MpiplPreservedState mpipl_state;
};
PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id);
@@ -290,4 +293,7 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
#define PNV11_OCC_SENSOR_BASE(chip) PNV10_OCC_SENSOR_BASE(chip)
+/* MPIPL helpers */
+void do_mpipl_preserve(PnvMachineState *pnv);
+
#endif /* PPC_PNV_H */
diff --git a/include/hw/ppc/pnv_mpipl.h b/include/hw/ppc/pnv_mpipl.h
new file mode 100644
index 000000000000..c544984dc76d
--- /dev/null
+++ b/include/hw/ppc/pnv_mpipl.h
@@ -0,0 +1,19 @@
+/*
+ * Emulation of MPIPL (Memory Preserving Initial Program Load), aka fadump
+ *
+ * SPDX-License-Identifier: GPL-2.0-or-later
+ */
+
+#ifndef PNV_MPIPL_H
+#define PNV_MPIPL_H
+
+#include "qemu/osdep.h"
+
+typedef struct MpiplPreservedState MpiplPreservedState;
+
+/* Preserved state to be saved in PnvMachineState */
+struct MpiplPreservedState {
+ bool is_next_boot_mpipl;
+};
+
+#endif
--
2.53.0
On 25/02/26 6:16 pm, Aditya Gupta wrote:
> During MPIPL (aka fadump), after a kernel crash, the kernel does
> opal_cec_reboot2 opal call, signifying an abnormal termination.
Minor nit..
> When OPAL recieves this opal call, it further triggers SBE S0 interrupt,
s/recieves/receives/
> to trigger a MPIPL boot.
>
> Currently S0 interrupt is unimplemented in QEMU.
>
> Implement S0 interrupt as 'pause_vcpus' + 'guest_reset' in QEMU, as the
> SBE's implementation of S0 seems to be basically "stop all clocks" and
> then "host reset".
>
> pause_vcpus is done in a later patch when register preserving support is
> added
>
> See 'stopClocksS0' in SBE source code for more information.
>
> Also log both S0 and S1 interrupts.
>
> Signed-off-by: Aditya Gupta <adityag@linux.ibm.com>
> ---
> hw/ppc/meson.build | 1 +
> hw/ppc/pnv_mpipl.c | 26 ++++++++++++++++++++++++++
> hw/ppc/pnv_sbe.c | 29 +++++++++++++++++++++++++++++
> include/hw/ppc/pnv.h | 6 ++++++
> include/hw/ppc/pnv_mpipl.h | 19 +++++++++++++++++++
> 5 files changed, 81 insertions(+)
> create mode 100644 hw/ppc/pnv_mpipl.c
> create mode 100644 include/hw/ppc/pnv_mpipl.h
>
> diff --git a/hw/ppc/meson.build b/hw/ppc/meson.build
> index f7dac87a2a48..c61fba4ec8f2 100644
> --- a/hw/ppc/meson.build
> +++ b/hw/ppc/meson.build
> @@ -56,6 +56,7 @@ ppc_ss.add(when: 'CONFIG_POWERNV', if_true: files(
> 'pnv_pnor.c',
> 'pnv_nest_pervasive.c',
> 'pnv_n1_chiplet.c',
> + 'pnv_mpipl.c',
> ))
> # PowerPC 4xx boards
> ppc_ss.add(when: 'CONFIG_PPC405', if_true: files(
> diff --git a/hw/ppc/pnv_mpipl.c b/hw/ppc/pnv_mpipl.c
> new file mode 100644
> index 000000000000..d8c9b7a428b7
> --- /dev/null
> +++ b/hw/ppc/pnv_mpipl.c
> @@ -0,0 +1,26 @@
> +/*
> + * Emulation of MPIPL (Memory Preserving Initial Program Load), aka fadump
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#include "qemu/osdep.h"
> +#include "system/runstate.h"
> +#include "hw/ppc/pnv.h"
> +#include "hw/ppc/pnv_mpipl.h"
> +
> +void do_mpipl_preserve(PnvMachineState *pnv)
> +{
> + /* Mark next boot as Memory-preserving boot */
> + pnv->mpipl_state.is_next_boot_mpipl = true;
> +
> + /*
> + * Do a guest reset.
> + * Next reset will see 'is_next_boot_mpipl' as true, and trigger MPIPL
> + *
> + * Requirement:
> + * GUEST_RESET is expected to NOT clear the memory, as is the case when
> + * this is merged
> + */
> + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET);
> +}
> diff --git a/hw/ppc/pnv_sbe.c b/hw/ppc/pnv_sbe.c
> index 247617338a0d..5a2b3342d199 100644
> --- a/hw/ppc/pnv_sbe.c
> +++ b/hw/ppc/pnv_sbe.c
> @@ -26,6 +26,9 @@
> #include "hw/ppc/pnv.h"
> #include "hw/ppc/pnv_xscom.h"
> #include "hw/ppc/pnv_sbe.h"
> +#include "hw/ppc/pnv_mpipl.h"
> +#include "system/cpus.h"
> +#include "system/runstate.h"
> #include "trace.h"
>
> /*
> @@ -113,11 +116,37 @@ static uint64_t pnv_sbe_power9_xscom_ctrl_read(void *opaque, hwaddr addr,
> static void pnv_sbe_power9_xscom_ctrl_write(void *opaque, hwaddr addr,
> uint64_t val, unsigned size)
> {
> + PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine());
> + PnvSBE *sbe = opaque;
> uint32_t offset = addr >> 3;
>
> trace_pnv_sbe_xscom_ctrl_write(addr, val);
>
> switch (offset) {
> + case SBE_CONTROL_REG_RW:
> + switch (val) {
> + case SBE_CONTROL_REG_S0:
> + qemu_log_mask(LOG_UNIMP, "SBE: S0 Interrupt triggered\n");
> +
> + pnv_sbe_set_host_doorbell(sbe, sbe->host_doorbell | SBE_HOST_RESPONSE_MASK);
> +
> + /* Preserve memory regions and CPU state, if MPIPL is registered */
> + do_mpipl_preserve(pnv);
> +
> + /*
> + * Control may not come back here as 'do_mpipl_preserve' triggers
> + * a guest reboot
> + */
> + break;
> + case SBE_CONTROL_REG_S1:
> + qemu_log_mask(LOG_UNIMP, "SBE: S1 Interrupt triggered\n");
> + break;
> + default:
> + qemu_log_mask(LOG_UNIMP,
> + "SBE: CONTROL_REG_RW: Unknown value: Ox%."
> + HWADDR_PRIx "\n", val);
> + }
> + break;
> default:
> qemu_log_mask(LOG_UNIMP, "SBE Unimplemented register: Ox%"
> HWADDR_PRIx "\n", addr >> 3);
> diff --git a/include/hw/ppc/pnv.h b/include/hw/ppc/pnv.h
> index 24f8843a4090..7d73629f112a 100644
> --- a/include/hw/ppc/pnv.h
> +++ b/include/hw/ppc/pnv.h
> @@ -25,6 +25,7 @@
> #include "hw/core/sysbus.h"
> #include "hw/ipmi/ipmi.h"
> #include "hw/ppc/pnv_pnor.h"
> +#include "hw/ppc/pnv_mpipl.h"
>
> #define TYPE_PNV_CHIP "pnv-chip"
>
> @@ -111,6 +112,8 @@ struct PnvMachineState {
>
> bool big_core;
> bool lpar_per_core;
> +
> + MpiplPreservedState mpipl_state;
> };
>
> PnvChip *pnv_get_chip(PnvMachineState *pnv, uint32_t chip_id);
> @@ -290,4 +293,7 @@ void pnv_bmc_set_pnor(IPMIBmc *bmc, PnvPnor *pnor);
>
> #define PNV11_OCC_SENSOR_BASE(chip) PNV10_OCC_SENSOR_BASE(chip)
>
> +/* MPIPL helpers */
> +void do_mpipl_preserve(PnvMachineState *pnv);
> +
> #endif /* PPC_PNV_H */
> diff --git a/include/hw/ppc/pnv_mpipl.h b/include/hw/ppc/pnv_mpipl.h
> new file mode 100644
> index 000000000000..c544984dc76d
> --- /dev/null
> +++ b/include/hw/ppc/pnv_mpipl.h
> @@ -0,0 +1,19 @@
> +/*
> + * Emulation of MPIPL (Memory Preserving Initial Program Load), aka fadump
> + *
> + * SPDX-License-Identifier: GPL-2.0-or-later
> + */
> +
> +#ifndef PNV_MPIPL_H
> +#define PNV_MPIPL_H
> +
> +#include "qemu/osdep.h"
> +
> +typedef struct MpiplPreservedState MpiplPreservedState;
> +
> +/* Preserved state to be saved in PnvMachineState */
> +struct MpiplPreservedState {
> + bool is_next_boot_mpipl;
> +};
> +
> +#endif
On 06/03/26 16:18, Hari Bathini wrote: > > On 25/02/26 6:16 pm, Aditya Gupta wrote: >> During MPIPL (aka fadump), after a kernel crash, the kernel does >> opal_cec_reboot2 opal call, signifying an abnormal termination. > > Minor nit.. > >> When OPAL recieves this opal call, it further triggers SBE S0 interrupt, > > s/recieves/receives/ Sure hari, will fix in v4. Thanks, - Aditya G
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