[v2] Add RISC-V big-endian target support

[PATCH v2 06/16] hw/riscv: Ensure proper ELF endian expectation

Posted by Djordje Todorovic 1 month, 2 weeks ago

load_elf_ram_sym has a `big_endian` paramater that notifies
it if the loaded elf file is expected to be LE or BE. This
paramater needs to be set based on target endianess to ensure
proper elf loading.
---
 hw/riscv/boot.c | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
index dc9f8a7327..6dab521a6b 100644
--- a/hw/riscv/boot.c
+++ b/hw/riscv/boot.c
@@ -166,7 +166,8 @@ hwaddr riscv_load_firmware(const char *firmware_filename,
 
     if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL,
                          &firmware_entry, NULL, &firmware_end, NULL,
-                         0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
+                         TARGET_BIG_ENDIAN ? ELFDATA2MSB : ELFDATA2LSB,
+                         EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
         *firmware_load_addr = firmware_entry;
         return firmware_end;
     }
@@ -248,8 +249,9 @@ void riscv_load_kernel(MachineState *machine,
      */
     kernel_size = load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NULL,
                                    &info->image_low_addr, &info->image_high_addr,
-                                   NULL, ELFDATA2LSB, EM_RISCV,
-                                   1, 0, NULL, true, sym_cb);
+                                   NULL,
+                                   TARGET_BIG_ENDIAN ? ELFDATA2MSB : ELFDATA2LSB,
+                                   EM_RISCV, 1, 0, NULL, true, sym_cb);
     if (kernel_size > 0) {
         info->kernel_size = kernel_size;
         goto out;
-- 
2.34.1

Re: [PATCH v2 06/16] hw/riscv: Ensure proper ELF endian expectation

Posted by Philippe Mathieu-Daudé 1 month, 1 week ago

On 25/2/26 11:20, Djordje Todorovic wrote:
> load_elf_ram_sym has a `big_endian` paramater that notifies
> it if the loaded elf file is expected to be LE or BE. This
> paramater needs to be set based on target endianess to ensure
> proper elf loading.
> ---
>   hw/riscv/boot.c | 8 +++++---
>   1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c
> index dc9f8a7327..6dab521a6b 100644
> --- a/hw/riscv/boot.c
> +++ b/hw/riscv/boot.c
> @@ -166,7 +166,8 @@ hwaddr riscv_load_firmware(const char *firmware_filename,
>   
>       if (load_elf_ram_sym(firmware_filename, NULL, NULL, NULL,
>                            &firmware_entry, NULL, &firmware_end, NULL,
> -                         0, EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
> +                         TARGET_BIG_ENDIAN ? ELFDATA2MSB : ELFDATA2LSB,
> +                         EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) {
>           *firmware_load_addr = firmware_entry;
>           return firmware_end;
>       }
> @@ -248,8 +249,9 @@ void riscv_load_kernel(MachineState *machine,
>        */
>       kernel_size = load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NULL,
>                                      &info->image_low_addr, &info->image_high_addr,
> -                                   NULL, ELFDATA2LSB, EM_RISCV,
> -                                   1, 0, NULL, true, sym_cb);
> +                                   NULL,
> +                                   TARGET_BIG_ENDIAN ? ELFDATA2MSB : ELFDATA2LSB,
> +                                   EM_RISCV, 1, 0, NULL, true, sym_cb);

See commit c36ec3a9655 ("hw/microblaze/s3adsp1800: Explicit CPU
endianness") and around.