On 25/2/26 11:20, Djordje Todorovic wrote:
> From: djtodoro <djordje.todorovic@htecgroup.com>
>
> RISC-V instructions are always little-endian. Use translator_ldl_end
> and translator_lduw_end with MO_LE instead of tswap on translator_ldl
> results.
OK, but this contradicts your previous own patch in this series:
[PATCH v2 04/16] target/riscv: Ensure LE instruction fetching
Squash them?
> ---
> target/riscv/translate.c | 15 ++++++---------
> 1 file changed, 6 insertions(+), 9 deletions(-)
>
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index 67dfb5f1c0..57dfc68220 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -23,8 +23,6 @@
> #include "exec/helper-proto.h"
> #include "exec/helper-gen.h"
> #include "exec/target_page.h"
> -#include "exec/tswap.h"
> -
> #include "exec/translator.h"
> #include "accel/tcg/cpu-ldst.h"
> #include "exec/translation-block.h"
> @@ -1255,13 +1253,13 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)
> * real one is 2 or 4 bytes. Instruction preload wouldn't trigger
> * additional page fault.
> */
> - opcode = tswap32(translator_ldl(env, &ctx->base, ctx->base.pc_next));
> + opcode = translator_ldl_end(env, &ctx->base, ctx->base.pc_next, MO_LE);
> } else {
> /*
> * For unaligned pc, instruction preload may trigger additional
> * page fault so we only load 2 bytes here.
> */
> - opcode = (uint32_t) tswap16(translator_lduw(env, &ctx->base, ctx->base.pc_next));
> + opcode = (uint32_t) translator_lduw_end(env, &ctx->base, ctx->base.pc_next, MO_LE);
> }
> ctx->ol = ctx->xl;
>
> @@ -1280,9 +1278,9 @@ static void decode_opc(CPURISCVState *env, DisasContext *ctx)
> } else {
> if (!pc_is_4byte_align) {
> /* Load last 2 bytes of instruction here */
> - uint16_t opcode_hi = translator_lduw(env, &ctx->base,
> - ctx->base.pc_next + 2);
> - opcode = deposit32(opcode, 16, 16, tswap16(opcode_hi));
> + uint16_t opcode_hi = translator_lduw_end(env, &ctx->base,
> + ctx->base.pc_next + 2, MO_LE);
> + opcode = deposit32(opcode, 16, 16, opcode_hi);
> }
> ctx->opcode = opcode;
>
> @@ -1397,8 +1395,7 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
>
> if (page_ofs > TARGET_PAGE_SIZE - MAX_INSN_LEN) {
> uint16_t next_insn =
> - translator_lduw(env, &ctx->base, ctx->base.pc_next);
> - next_insn = tswap16(next_insn);
> + translator_lduw_end(env, &ctx->base, ctx->base.pc_next, MO_LE);
> int len = insn_len(next_insn);
>
> if (!translator_is_same_page(&ctx->base, ctx->base.pc_next + len - 1)) {