[v2] Add RISC-V big-endian target support

[PATCH v2 09/16] arch/riscv: Set UBE bit on BE target

Posted by Djordje Todorovic 1 month, 2 weeks ago

When the RISC-V target is built as big-endian, ensure that is signaled
in mstatus via UBE bit.
---
 target/riscv/cpu.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index e95eea0249..0e24f2cbcd 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -716,6 +716,9 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
             env->mstatus = set_field(env->mstatus, MSTATUS_MDT, 1);
         }
     }
+#if defined(TARGET_BIG_ENDIAN)
+    env->mstatus |= MSTATUS_UBE;
+#endif
     env->mcause = 0;
     env->miclaim = MIP_SGEIP;
     env->pc = env->resetvec;
-- 
2.34.1

Re: [PATCH v2 09/16] arch/riscv: Set UBE bit on BE target

Posted by Philippe Mathieu-Daudé 1 month, 1 week ago

On 25/2/26 11:20, Djordje Todorovic wrote:
> When the RISC-V target is built as big-endian, ensure that is signaled
> in mstatus via UBE bit.
> ---
>   target/riscv/cpu.c | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index e95eea0249..0e24f2cbcd 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -716,6 +716,9 @@ static void riscv_cpu_reset_hold(Object *obj, ResetType type)
>               env->mstatus = set_field(env->mstatus, MSTATUS_MDT, 1);
>           }
>       }
> +#if defined(TARGET_BIG_ENDIAN)
> +    env->mstatus |= MSTATUS_UBE;
> +#endif

You should update mo_endian_env() instead IMO.