Currently, we check for register multiwrites during packet decode. The
downside of this approach is that it only checks a single destination
register for each instruction.  During analyze_packet, we can check
for more than one instruction.  Further, we can check for different
types of registers.  This series adds checks for HVX v-registers and
q-registers.

Note that multiple writes to a predicate register are allowed on Hexagon.

Taylor Simpson (8):
  Hexagon (target/hexagon) Move code out of gen_start_packet
  Hexagon (target/hexagon) Check for GPR multiwrite in analyze_packet
  Hexagon (tests/tcg/hexagon) Add tests for multi-destination
    instructions
  Hexagon (target/hexagon) Check for vreg multiwrite in analyze_packet
  Hexagon (tests/tcg/hexagon) Add tests for vreg multiple writes
  Hexagon (target/hexagon) Check for qreg multiwrite in analyze_packet
  Hexagon (tests/tcg/hexagon) Add tests for qreg multiple writes
  Hexagon (target/hexagon) Remove old way of detecting register
    multiwrites

 target/hexagon/insn.h               |   4 -
 target/hexagon/translate.h          |  25 +++++-
 target/hexagon/decode.c             |  54 ------------
 target/hexagon/translate.c          |  77 ++++++++++++-----
 tests/tcg/hexagon/multiple-writes.c | 129 ++++++++++++++++++++++++++++
 target/hexagon/gen_trans_funcs.py   |  10 ---
 tests/tcg/hexagon/Makefile.target   |   1 +
 7 files changed, 210 insertions(+), 90 deletions(-)

-- 
2.43.0

On Mon, Feb 23, 2026 at 2:56 PM Taylor Simpson <ltaylorsimpson@gmail.com>
wrote:

> Currently, we check for register multiwrites during packet decode. The
> downside of this approach is that it only checks a single destination
> register for each instruction.  During analyze_packet, we can check
> for more than one instruction.  Further, we can check for different
> types of registers.  This series adds checks for HVX v-registers and
> q-registers.
>
> Note that multiple writes to a predicate register are allowed on Hexagon.
>
> Taylor Simpson (8):
>   Hexagon (target/hexagon) Move code out of gen_start_packet
>   Hexagon (target/hexagon) Check for GPR multiwrite in analyze_packet
>   Hexagon (tests/tcg/hexagon) Add tests for multi-destination
>     instructions
>   Hexagon (target/hexagon) Check for vreg multiwrite in analyze_packet
>   Hexagon (tests/tcg/hexagon) Add tests for vreg multiple writes
>   Hexagon (target/hexagon) Check for qreg multiwrite in analyze_packet
>   Hexagon (tests/tcg/hexagon) Add tests for qreg multiple writes
>   Hexagon (target/hexagon) Remove old way of detecting register
>     multiwrites
>
>  target/hexagon/insn.h               |   4 -
>  target/hexagon/translate.h          |  25 +++++-
>  target/hexagon/decode.c             |  54 ------------
>  target/hexagon/translate.c          |  77 ++++++++++++-----
>  tests/tcg/hexagon/multiple-writes.c | 129 ++++++++++++++++++++++++++++
>  target/hexagon/gen_trans_funcs.py   |  10 ---
>  tests/tcg/hexagon/Makefile.target   |   1 +
>  7 files changed, 210 insertions(+), 90 deletions(-)
>
>
For this entire series:

Tested-by: Brian Cain <brian.cain@oss.qualcomm.com>
Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>



> --
> 2.43.0
>
>