The CPU has several interrupt sources which are exposed as GICv5
PPIs. For QEMU, this means the generic timers and the PMU.
In GICv3, we implemented these as qemu_irq lines which connect up to
the external interrupt controller device. In a GICv5, the PPIs are
handled entirely inside the CPU interface, so there are no external
signals. Instead we provide a gicv5_update_ppi_state() function
which the emulated timer and PMU code uses to tell the CPU interface
about the new state of the PPI source.
We make the GICv5 function a no-op if there is no GICv5 present, so
that calling code can do both "update the old irq lines" and "update
the GICv5 PPI" without having to add conditionals. (In a GICv5
system the old irq lines won't be connected to anything, so the
qemu_set_irq() will be a no-op.)
Updating PPIs via either mechanism is unnecessary in user-only mode;
we got away with not ifdeffing this away before because
qemu_set_irq() is built for user-only mode, but since the GICv5 cpuif
code is system-emulation only, we do need an ifdef now.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
target/arm/cpregs-pmu.c | 9 +++++++--
target/arm/helper.c | 20 ++++++++++++++++++++
target/arm/internals.h | 6 ++++++
target/arm/tcg/gicv5-cpuif.c | 28 ++++++++++++++++++++++++++++
target/arm/tcg/trace-events | 1 +
5 files changed, 62 insertions(+), 2 deletions(-)
diff --git a/target/arm/cpregs-pmu.c b/target/arm/cpregs-pmu.c
index 47e1e4652b..46df6597b1 100644
--- a/target/arm/cpregs-pmu.c
+++ b/target/arm/cpregs-pmu.c
@@ -428,9 +428,14 @@ static bool pmu_counter_enabled(CPUARMState *env, uint8_t counter)
static void pmu_update_irq(CPUARMState *env)
{
+#ifndef CONFIG_USER_ONLY
ARMCPU *cpu = env_archcpu(env);
- qemu_set_irq(cpu->pmu_interrupt, (env->cp15.c9_pmcr & PMCRE) &&
- (env->cp15.c9_pminten & env->cp15.c9_pmovsr));
+ bool level = (env->cp15.c9_pmcr & PMCRE) &&
+ (env->cp15.c9_pminten & env->cp15.c9_pmovsr);
+
+ gicv5_update_ppi_state(env, GICV5_PPI_PMUIRQ, level);
+ qemu_set_irq(cpu->pmu_interrupt, level);
+#endif
}
static bool pmccntr_clockdiv_enabled(CPUARMState *env)
diff --git a/target/arm/helper.c b/target/arm/helper.c
index 5e7cc039aa..a6bad8eba3 100644
--- a/target/arm/helper.c
+++ b/target/arm/helper.c
@@ -1348,6 +1348,21 @@ uint64_t gt_get_countervalue(CPUARMState *env)
return qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) / gt_cntfrq_period_ns(cpu);
}
+static void gt_update_gicv5_ppi(CPUARMState *env, int timeridx, bool level)
+{
+ static int timeridx_to_ppi[] = {
+ [GTIMER_PHYS] = GICV5_PPI_CNTP,
+ [GTIMER_VIRT] = GICV5_PPI_CNTV,
+ [GTIMER_HYP] = GICV5_PPI_CNTHP,
+ [GTIMER_SEC] = GICV5_PPI_CNTPS,
+ [GTIMER_HYPVIRT] = GICV5_PPI_CNTHV,
+ [GTIMER_S_EL2_PHYS] = GICV5_PPI_CNTHPS,
+ [GTIMER_S_EL2_VIRT] = GICV5_PPI_CNTHVS,
+ };
+
+ gicv5_update_ppi_state(env, timeridx_to_ppi[timeridx], level);
+}
+
static void gt_update_irq(ARMCPU *cpu, int timeridx)
{
CPUARMState *env = &cpu->env;
@@ -1366,6 +1381,11 @@ static void gt_update_irq(ARMCPU *cpu, int timeridx)
irqstate = 0;
}
+ /*
+ * We update both the GICv5 PPI and the external-GIC irq line
+ * (whichever of the two mechanisms is unused will do nothing)
+ */
+ gt_update_gicv5_ppi(env, timeridx, irqstate);
qemu_set_irq(cpu->gt_timer_outputs[timeridx], irqstate);
trace_arm_gt_update_irq(timeridx, irqstate);
}
diff --git a/target/arm/internals.h b/target/arm/internals.h
index 9bde58cf00..afe893f49d 100644
--- a/target/arm/internals.h
+++ b/target/arm/internals.h
@@ -1800,6 +1800,12 @@ void define_gcs_cpregs(ARMCPU *cpu);
/* Add the cpreg definitions for the GICv5 CPU interface */
void define_gicv5_cpuif_regs(ARMCPU *cpu);
+/*
+ * Update the state of the given GICv5 PPI for this CPU. Does nothing
+ * if the GICv5 is not present.
+ */
+void gicv5_update_ppi_state(CPUARMState *env, int ppi, bool level);
+
/* Effective value of MDCR_EL2 */
static inline uint64_t arm_mdcr_el2_eff(CPUARMState *env)
{
diff --git a/target/arm/tcg/gicv5-cpuif.c b/target/arm/tcg/gicv5-cpuif.c
index 79203a3478..d30617d143 100644
--- a/target/arm/tcg/gicv5-cpuif.c
+++ b/target/arm/tcg/gicv5-cpuif.c
@@ -314,6 +314,34 @@ void gicv5_forward_interrupt(ARMCPU *cpu, GICv5Domain domain)
gicv5_update_irq_fiq(&cpu->env);
}
+void gicv5_update_ppi_state(CPUARMState *env, int ppi, bool level)
+{
+ /*
+ * Update the state of the given PPI (which is connected to some
+ * CPU-internal source of interrupts, like the timers).
+ * We can assume that the PPI is fixed as level-triggered,
+ * which means that its pending state exactly tracks the input
+ * (and the guest cannot separately change the pending state,
+ * because the pending bits are RO).
+ */
+ int oldlevel;
+
+ if (!cpu_isar_feature(aa64_gcie, env_archcpu(env))) {
+ return;
+ }
+
+ /* The architected PPIs are 0..63, so in the first PPI register. */
+ assert(ppi >= 0 && ppi < 64);
+ oldlevel = extract64(env->gicv5_cpuif.ppi_pend[0], ppi, 1);
+ if (oldlevel != level) {
+ trace_gicv5_update_ppi_state(ppi, level);
+
+ env->gicv5_cpuif.ppi_pend[0] =
+ deposit64(env->gicv5_cpuif.ppi_pend[0], ppi, 1, level);
+ gic_recalc_ppi_hppi(env);
+ }
+}
+
static void gic_cddis_write(CPUARMState *env, const ARMCPRegInfo *ri,
uint64_t value)
{
diff --git a/target/arm/tcg/trace-events b/target/arm/tcg/trace-events
index 2bfa8fc552..bf1803c872 100644
--- a/target/arm/tcg/trace-events
+++ b/target/arm/tcg/trace-events
@@ -8,3 +8,4 @@ gicv5_gicr_cdia(int domain, uint32_t id) "domain %d CDIA acknowledge of interrup
gicv5_cdeoi(int domain) "domain %d CDEOI performing priority drop"
gicv5_cddi(int domain, uint32_t id) "domain %d CDDI deactivating interrupt ID 0x%x"
gicv5_update_irq_fiq(bool irq, bool fiq, bool nmi) "now IRQ %d FIQ %d NMI %d"
+gicv5_update_ppi_state(int ppi, bool level) "PPI %d source level now %d"
--
2.43.0