The IRS_SYNCR register is used by software to request synchronization
of interrupt events. This means that in-flight interrupt events are
guaranteed to have been delivered.
Since QEMU's implementation is entirely synchronous, syncs are a
no-op for us. This means we can ignore writes to IRS_SYNCR and
always report "sync complete" via the IDLE bit in IRS_SYNC_STATUSR.
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
hw/intc/arm_gicv5.c | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/hw/intc/arm_gicv5.c b/hw/intc/arm_gicv5.c
index 5f4c4158c4..d0ba8fe669 100644
--- a/hw/intc/arm_gicv5.c
+++ b/hw/intc/arm_gicv5.c
@@ -1047,6 +1047,10 @@ static bool config_readl(GICv5 *s, GICv5Domain domain, hwaddr offset,
case A_IRS_CR1:
*data = cs->irs_cr1[domain];
return true;
+ case A_IRS_SYNC_STATUSR:
+ /* Sync is a no-op for QEMU: we are always IDLE */
+ *data = R_IRS_SYNC_STATUSR_IDLE_MASK;
+ return true;
}
return false;
@@ -1132,6 +1136,9 @@ static bool config_writel(GICv5 *s, GICv5Domain domain, hwaddr offset,
case A_IRS_CR1:
cs->irs_cr1[domain] = data;
return true;
+ case A_IRS_SYNCR:
+ /* Sync is a no-op for QEMU: ignore write */
+ return true;
}
return false;
}
--
2.43.0