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[PATCH v2 28/50] target/riscv: Remove unnecessary target_ulong type uses

Philippe Mathieu-Daudé posted 50 patches 1 month ago
Maintainers: Laurent Vivier <laurent@vivier.eu>, Pierrick Bouvier <pierrick.bouvier@linaro.org>, Michael Rolnik <mrolnik@gmail.com>, "Alex Bennée" <alex.bennee@linaro.org>, "Philippe Mathieu-Daudé" <philmd@linaro.org>, Eduardo Habkost <eduardo@habkost.net>, Marcel Apfelbaum <marcel.apfelbaum@gmail.com>, Yanan Wang <wangyanan55@huawei.com>, Zhao Liu <zhao1.liu@intel.com>, "Dr. David Alan Gilbert" <dave@treblig.org>, Richard Henderson <richard.henderson@linaro.org>, Brian Cain <brian.cain@oss.qualcomm.com>, Paolo Bonzini <pbonzini@redhat.com>, Song Gao <gaosong@loongson.cn>, "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, Aurelien Jarno <aurelien@aurel32.net>, Jiaxun Yang <jiaxun.yang@flygoat.com>, Aleksandar Rikalo <arikalo@gmail.com>, Stafford Horne <shorne@gmail.com>, Nicholas Piggin <npiggin@gmail.com>, Chinmay Rath <rathc@linux.ibm.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Yoshinori Sato <yoshinori.sato@nifty.com>, Ilya Leoshkevich <iii@linux.ibm.com>, David Hildenbrand <david@kernel.org>, Thomas Huth <thuth@redhat.com>, Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>, Artyom Tarasenko <atar4qemu@gmail.com>, Bastian Koppelmann <kbastian@rumtueddeln.de>
[PATCH v2 28/50] target/riscv: Remove unnecessary target_ulong type uses
Posted by Philippe Mathieu-Daudé 1 month ago 
Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/riscv/gdbstub.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
index f89b20ea84a..a053009ccd3 100644
--- a/target/riscv/gdbstub.c
+++ b/target/riscv/gdbstub.c
@@ -52,7 +52,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
     RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
-    target_ulong tmp;
+    uint64_t tmp;
 
     if (n < 32) {
         tmp = env->gpr[n];
@@ -80,7 +80,7 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
     RISCVCPU *cpu = RISCV_CPU(cs);
     CPURISCVState *env = &cpu->env;
     int length = 0;
-    target_ulong tmp;
+    uint64_t tmp;
 
     switch (mcc->def->misa_mxl_max) {
     case MXL_RV32:
@@ -194,7 +194,7 @@ static int riscv_gdb_set_csr(CPUState *cs, uint8_t *mem_buf, int n)
     const unsigned regsz = riscv_cpu_is_32bit(cpu) ? 4 : 8;
 
     if (n < CSR_TABLE_SIZE) {
-        target_ulong val = ldn_p(mem_buf, regsz);
+        uint64_t val = ldn_p(mem_buf, regsz);
         int result;
 
         result = riscv_csrrw_debug(env, n, NULL, val, -1);
@@ -215,7 +215,7 @@ static int riscv_gdb_get_virtual(CPUState *cs, GByteArray *buf, int n)
         CPURISCVState *env = &cpu->env;
 
         /* Per RiscV debug spec v1.0.0 rc4 */
-        target_ulong vbit = (env->virt_enabled) ? BIT(2) : 0;
+        uint32_t vbit = (env->virt_enabled) ? BIT(2) : 0;
 
         return gdb_get_regl(buf, env->priv | vbit);
 #endif
-- 
2.52.0
Re: [PATCH v2 28/50] target/riscv: Remove unnecessary target_ulong type uses
Posted by Chao Liu 4 weeks, 1 day ago 
On Thu, Feb 19, 2026 at 08:19:30PM +0100, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>  target/riscv/gdbstub.c | 8 ++++----
>  1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index f89b20ea84a..a053009ccd3 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -52,7 +52,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
>      RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
>      RISCVCPU *cpu = RISCV_CPU(cs);
>      CPURISCVState *env = &cpu->env;
> -    target_ulong tmp;
> +    uint64_t tmp;
>  
>      if (n < 32) {
>          tmp = env->gpr[n];
> @@ -80,7 +80,7 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
>      RISCVCPU *cpu = RISCV_CPU(cs);
>      CPURISCVState *env = &cpu->env;
>      int length = 0;
> -    target_ulong tmp;
> +    uint64_t tmp;
>  
>      switch (mcc->def->misa_mxl_max) {
>      case MXL_RV32:
> @@ -194,7 +194,7 @@ static int riscv_gdb_set_csr(CPUState *cs, uint8_t *mem_buf, int n)
>      const unsigned regsz = riscv_cpu_is_32bit(cpu) ? 4 : 8;
>  
>      if (n < CSR_TABLE_SIZE) {
> -        target_ulong val = ldn_p(mem_buf, regsz);
> +        uint64_t val = ldn_p(mem_buf, regsz);
>          int result;
>  
>          result = riscv_csrrw_debug(env, n, NULL, val, -1);
> @@ -215,7 +215,7 @@ static int riscv_gdb_get_virtual(CPUState *cs, GByteArray *buf, int n)
>          CPURISCVState *env = &cpu->env;
>  
>          /* Per RiscV debug spec v1.0.0 rc4 */
> -        target_ulong vbit = (env->virt_enabled) ? BIT(2) : 0;
> +        uint32_t vbit = (env->virt_enabled) ? BIT(2) : 0;
>  
>          return gdb_get_regl(buf, env->priv | vbit);
>  #endif
> -- 
> 2.52.0
> 
> 

Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>

Thanks,
Chao
Re: [PATCH v2 28/50] target/riscv: Remove unnecessary target_ulong type uses
Posted by Daniel Henrique Barboza 1 month ago 

On 2/19/2026 4:19 PM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---

Reviewed-by: Daniel Henrique Barboza <daniel.barboza@oss.qualcomm.com>

>   target/riscv/gdbstub.c | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
> 
> diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c
> index f89b20ea84a..a053009ccd3 100644
> --- a/target/riscv/gdbstub.c
> +++ b/target/riscv/gdbstub.c
> @@ -52,7 +52,7 @@ int riscv_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
>       RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
>       RISCVCPU *cpu = RISCV_CPU(cs);
>       CPURISCVState *env = &cpu->env;
> -    target_ulong tmp;
> +    uint64_t tmp;
>   
>       if (n < 32) {
>           tmp = env->gpr[n];
> @@ -80,7 +80,7 @@ int riscv_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
>       RISCVCPU *cpu = RISCV_CPU(cs);
>       CPURISCVState *env = &cpu->env;
>       int length = 0;
> -    target_ulong tmp;
> +    uint64_t tmp;
>   
>       switch (mcc->def->misa_mxl_max) {
>       case MXL_RV32:
> @@ -194,7 +194,7 @@ static int riscv_gdb_set_csr(CPUState *cs, uint8_t *mem_buf, int n)
>       const unsigned regsz = riscv_cpu_is_32bit(cpu) ? 4 : 8;
>   
>       if (n < CSR_TABLE_SIZE) {
> -        target_ulong val = ldn_p(mem_buf, regsz);
> +        uint64_t val = ldn_p(mem_buf, regsz);
>           int result;
>   
>           result = riscv_csrrw_debug(env, n, NULL, val, -1);
> @@ -215,7 +215,7 @@ static int riscv_gdb_get_virtual(CPUState *cs, GByteArray *buf, int n)
>           CPURISCVState *env = &cpu->env;
>   
>           /* Per RiscV debug spec v1.0.0 rc4 */
> -        target_ulong vbit = (env->virt_enabled) ? BIT(2) : 0;
> +        uint32_t vbit = (env->virt_enabled) ? BIT(2) : 0;
>   
>           return gdb_get_regl(buf, env->priv | vbit);
>   #endif
Re: [PATCH v2 28/50] target/riscv: Remove unnecessary target_ulong type uses
Posted by Pierrick Bouvier 1 month ago 
On 2/19/26 11:19 AM, Philippe Mathieu-Daudé wrote:
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/riscv/gdbstub.c | 8 ++++----
>   1 file changed, 4 insertions(+), 4 deletions(-)
> 

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>

Patchew 2.1-devel-ea86937

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