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[PATCH v1] hw/char/cadence_uart: Add BXRS register

Kuan-Jui Chiu posted 1 patch 1 month, 4 weeks ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20260212104432.4168886-1-kchiu@axiado.com
Maintainers: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, Alistair Francis <alistair@alistair23.me>, Peter Maydell <peter.maydell@linaro.org>, "Marc-André Lureau" <marcandre.lureau@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>
hw/char/cadence_uart.c         | 2 ++
include/hw/char/cadence_uart.h | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
[PATCH v1] hw/char/cadence_uart: Add BXRS register
Posted by Kuan-Jui Chiu 1 month, 4 weeks ago 
The new CADENCE UART driver in upstream kernel access BXRS register
This patch adds BXRS (RX FIFO byte status register) or there would be
kernel panic if user are using the new CADENCE UART driver

Signed-off-by: Kuan-Jui Chiu <kchiu@axiado.com>
---
 hw/char/cadence_uart.c         | 2 ++
 include/hw/char/cadence_uart.h | 2 +-
 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index eff6a3c4d1..f57cad57a8 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -120,6 +120,7 @@
 #define R_PMIN     (0x3C/4)
 #define R_PWID     (0x40/4)
 #define R_TTRIG    (0x44/4)
+#define R_RXBS     (0x48/4)
 
 
 static void uart_update_status(CadenceUARTState *s)
@@ -523,6 +524,7 @@ static void cadence_uart_reset_init(Object *obj, ResetType type)
     s->r[R_BRGR] = 0x0000028B;
     s->r[R_BDIV] = 0x0000000F;
     s->r[R_TTRIG] = 0x00000020;
+    s->r[R_RXBS] = 0;
 }
 
 static void cadence_uart_reset_hold(Object *obj, ResetType type)
diff --git a/include/hw/char/cadence_uart.h b/include/hw/char/cadence_uart.h
index 751a751248..0f97e19112 100644
--- a/include/hw/char/cadence_uart.h
+++ b/include/hw/char/cadence_uart.h
@@ -29,7 +29,7 @@
 #define CADENCE_UART_RX_FIFO_SIZE           16
 #define CADENCE_UART_TX_FIFO_SIZE           16
 
-#define CADENCE_UART_R_MAX (0x48/4)
+#define CADENCE_UART_R_MAX (0x4C/4)
 
 #define TYPE_CADENCE_UART "cadence_uart"
 OBJECT_DECLARE_SIMPLE_TYPE(CadenceUARTState, CADENCE_UART)
-- 
2.34.1
Re: [PATCH v1] hw/char/cadence_uart: Add BXRS register
Posted by Peter Maydell 1 month, 3 weeks ago 
On Thu, 12 Feb 2026 at 10:47, Kuan-Jui Chiu <kchiu@axiado.com> wrote:
>
> The new CADENCE UART driver in upstream kernel access BXRS register
> This patch adds BXRS (RX FIFO byte status register) or there would be
> kernel panic if user are using the new CADENCE UART driver
>
> Signed-off-by: Kuan-Jui Chiu <kchiu@axiado.com>

Hi; thanks for this patch.

> diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
> index eff6a3c4d1..f57cad57a8 100644
> --- a/hw/char/cadence_uart.c
> +++ b/hw/char/cadence_uart.c
> @@ -120,6 +120,7 @@
>  #define R_PMIN     (0x3C/4)
>  #define R_PWID     (0x40/4)
>  #define R_TTRIG    (0x44/4)
> +#define R_RXBS     (0x48/4)

Where is this register documented? The cadence_uart.c file
references the Zynq 7000 Soc TRM UG585; its URL for that
is out of date, but looking at the copy on the AMD website,
there is a table giving the register summary for the UART:
https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/UART-Controller-UART
and it lists only registers from offsets 0 to 0x44.

thanks
-- PMM
Re: [PATCH v1] hw/char/cadence_uart: Add BXRS register
Posted by Kuan-Jui Chiu 1 month, 1 week ago 
Hi

I was referring this commit of upstream kernel which xilinx added BXRS 
register in Cadence UART driver
serial: xuartps: Adds RXBS register support for zynqmp · 
torvalds/linux@3816b2f 
<https://github.com/torvalds/linux/commit/3816b2f886d0918d8a8ae593b2db203ab905a889>

Peter Maydell 於 2026/2/16 下午 06:53 寫道:
> CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.
>
>
> On Thu, 12 Feb 2026 at 10:47, Kuan-Jui Chiu <kchiu@axiado.com> wrote:
>> The new CADENCE UART driver in upstream kernel access BXRS register
>> This patch adds BXRS (RX FIFO byte status register) or there would be
>> kernel panic if user are using the new CADENCE UART driver
>>
>> Signed-off-by: Kuan-Jui Chiu <kchiu@axiado.com>
> Hi; thanks for this patch.
>
>> diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
>> index eff6a3c4d1..f57cad57a8 100644
>> --- a/hw/char/cadence_uart.c
>> +++ b/hw/char/cadence_uart.c
>> @@ -120,6 +120,7 @@
>>   #define R_PMIN     (0x3C/4)
>>   #define R_PWID     (0x40/4)
>>   #define R_TTRIG    (0x44/4)
>> +#define R_RXBS     (0x48/4)
> Where is this register documented? The cadence_uart.c file
> references the Zynq 7000 Soc TRM UG585; its URL for that
> is out of date, but looking at the copy on the AMD website,
> there is a table giving the register summary for the UART:
> https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/UART-Controller-UART
> and it lists only registers from offsets 0 to 0x44.
>
> thanks
> -- PMM
Re: [PATCH v1] hw/char/cadence_uart: Add BXRS register
Posted by Edgar E. Iglesias 1 month, 1 week ago 
On Tue, Mar 3, 2026 at 2:33 AM Kuan-Jui Chiu <kchiu@axiado.com> wrote:

> Hi
>
> I was referring this commit of upstream kernel which xilinx added BXRS
> register in Cadence UART driver
> serial: xuartps: Adds RXBS register support for zynqmp ·
> torvalds/linux@3816b2f
> <
> https://github.com/torvalds/linux/commit/3816b2f886d0918d8a8ae593b2db203ab905a889
> >
>
> Peter Maydell 於 2026/2/16 下午 06:53 寫道:
> > CAUTION: This email originated from outside of the organization. Do not
> click links or open attachments unless you recognize the sender and know
> the content is safe.
> >
> >
> > On Thu, 12 Feb 2026 at 10:47, Kuan-Jui Chiu <kchiu@axiado.com> wrote:
> >> The new CADENCE UART driver in upstream kernel access BXRS register
> >> This patch adds BXRS (RX FIFO byte status register) or there would be
> >> kernel panic if user are using the new CADENCE UART driver
> >>
> >> Signed-off-by: Kuan-Jui Chiu <kchiu@axiado.com>
> > Hi; thanks for this patch.
> >
> >> diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
> >> index eff6a3c4d1..f57cad57a8 100644
> >> --- a/hw/char/cadence_uart.c
> >> +++ b/hw/char/cadence_uart.c
> >> @@ -120,6 +120,7 @@
> >>   #define R_PMIN     (0x3C/4)
> >>   #define R_PWID     (0x40/4)
> >>   #define R_TTRIG    (0x44/4)
> >> +#define R_RXBS     (0x48/4)
> > Where is this register documented? The cadence_uart.c file
> > references the Zynq 7000 Soc TRM UG585; its URL for that
> > is out of date, but looking at the copy on the AMD website,
> > there is a table giving the register summary for the UART:
> >
> https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/UART-Controller-UART
> > and it lists only registers from offsets 0 to 0x44.
> >
> > thanks
> > -- PMM
>


Hi,

There's documentation here for zynqmp:
https://docs.amd.com/r/en-US/ug1087-zynq-ultrascale-registers/Rx_FIFO_byte_status-UART-Register

I haven't looked to carefully, it may be a register that didn't exist in
the version of the UART on zynq and was added in the version of the uart in
the zynqmp.

Cheers,
Edgar
Re: [PATCH v1] hw/char/cadence_uart: Add BXRS register
Posted by Peter Maydell 1 month, 1 week ago 
On Tue, 3 Mar 2026 at 18:32, Edgar E. Iglesias <edgar.iglesias@gmail.com> wrote:
>
>
>
> On Tue, Mar 3, 2026 at 2:33 AM Kuan-Jui Chiu <kchiu@axiado.com> wrote:
>>
>> Hi
>>
>> I was referring this commit of upstream kernel which xilinx added BXRS
>> register in Cadence UART driver
>> serial: xuartps: Adds RXBS register support for zynqmp ·
>> torvalds/linux@3816b2f
>> <https://github.com/torvalds/linux/commit/3816b2f886d0918d8a8ae593b2db203ab905a889>
>>
>> Peter Maydell 於 2026/2/16 下午 06:53 寫道:

>> > Where is this register documented? The cadence_uart.c file
>> > references the Zynq 7000 Soc TRM UG585; its URL for that
>> > is out of date, but looking at the copy on the AMD website,
>> > there is a table giving the register summary for the UART:
>> > https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/UART-Controller-UART
>> > and it lists only registers from offsets 0 to 0x44.

> There's documentation here for zynqmp:
> https://docs.amd.com/r/en-US/ug1087-zynq-ultrascale-registers/Rx_FIFO_byte_status-UART-Register
>
> I haven't looked to carefully, it may be a register that didn't exist in the version of the UART on zynq and was added in the version of the uart in the zynqmp.

Thanks. On the subject of Xilinx specs, do you have an opinion on
https://gitlab.com/qemu-project/qemu/-/issues/3297 ?
Our Xilinx AXI ethernet device model lets software write to
the PHY registers for the PHY ID, and it's not clear to me
whether these registers are supposed to be read-only or not.

thanks
-- PMM
Re: [PATCH v1] hw/char/cadence_uart: Add BXRS register
Posted by Edgar E. Iglesias 1 month, 1 week ago 
On Tue, Mar 3, 2026 at 12:44 PM Peter Maydell <peter.maydell@linaro.org>
wrote:

> On Tue, 3 Mar 2026 at 18:32, Edgar E. Iglesias <edgar.iglesias@gmail.com>
> wrote:
> >
> >
> >
> > On Tue, Mar 3, 2026 at 2:33 AM Kuan-Jui Chiu <kchiu@axiado.com> wrote:
> >>
> >> Hi
> >>
> >> I was referring this commit of upstream kernel which xilinx added BXRS
> >> register in Cadence UART driver
> >> serial: xuartps: Adds RXBS register support for zynqmp ·
> >> torvalds/linux@3816b2f
> >> <
> https://github.com/torvalds/linux/commit/3816b2f886d0918d8a8ae593b2db203ab905a889
> >
> >>
> >> Peter Maydell 於 2026/2/16 下午 06:53 寫道:
>
> >> > Where is this register documented? The cadence_uart.c file
> >> > references the Zynq 7000 Soc TRM UG585; its URL for that
> >> > is out of date, but looking at the copy on the AMD website,
> >> > there is a table giving the register summary for the UART:
> >> >
> https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/UART-Controller-UART
> >> > and it lists only registers from offsets 0 to 0x44.
>
> > There's documentation here for zynqmp:
> >
> https://docs.amd.com/r/en-US/ug1087-zynq-ultrascale-registers/Rx_FIFO_byte_status-UART-Register
> >
> > I haven't looked to carefully, it may be a register that didn't exist in
> the version of the UART on zynq and was added in the version of the uart in
> the zynqmp.
>
> Thanks. On the subject of Xilinx specs, do you have an opinion on
> https://gitlab.com/qemu-project/qemu/-/issues/3297 ?
> Our Xilinx AXI ethernet device model lets software write to
> the PHY registers for the PHY ID, and it's not clear to me
> whether these registers are supposed to be read-only or not.
>
>
Yes, they should be read-only, there's probably more registers and fields
that have the wrong access restrictions as well. The PHY model is super
simple, created just to get guests to not get stuck on boot or fail to use
the PHY...

IIRC, there's been several attempts on list to create a better MDIO/PHY
interface with shared PHY models but never got merged.

Cheers,
Edgar
Re: [PATCH v1] hw/char/cadence_uart: Add BXRS register
Posted by Edgar E. Iglesias 1 month, 1 week ago 
On Tue, Mar 3, 2026 at 12:59 PM Edgar E. Iglesias <edgar.iglesias@gmail.com>
wrote:

>
>
> On Tue, Mar 3, 2026 at 12:44 PM Peter Maydell <peter.maydell@linaro.org>
> wrote:
>
>> On Tue, 3 Mar 2026 at 18:32, Edgar E. Iglesias <edgar.iglesias@gmail.com>
>> wrote:
>> >
>> >
>> >
>> > On Tue, Mar 3, 2026 at 2:33 AM Kuan-Jui Chiu <kchiu@axiado.com> wrote:
>> >>
>> >> Hi
>> >>
>> >> I was referring this commit of upstream kernel which xilinx added BXRS
>> >> register in Cadence UART driver
>> >> serial: xuartps: Adds RXBS register support for zynqmp ·
>> >> torvalds/linux@3816b2f
>> >> <
>> https://github.com/torvalds/linux/commit/3816b2f886d0918d8a8ae593b2db203ab905a889
>> >
>> >>
>> >> Peter Maydell 於 2026/2/16 下午 06:53 寫道:
>>
>> >> > Where is this register documented? The cadence_uart.c file
>> >> > references the Zynq 7000 Soc TRM UG585; its URL for that
>> >> > is out of date, but looking at the copy on the AMD website,
>> >> > there is a table giving the register summary for the UART:
>> >> >
>> https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM/UART-Controller-UART
>> >> > and it lists only registers from offsets 0 to 0x44.
>>
>> > There's documentation here for zynqmp:
>> >
>> https://docs.amd.com/r/en-US/ug1087-zynq-ultrascale-registers/Rx_FIFO_byte_status-UART-Register
>> >
>> > I haven't looked to carefully, it may be a register that didn't exist
>> in the version of the UART on zynq and was added in the version of the uart
>> in the zynqmp.
>>
>> Thanks. On the subject of Xilinx specs, do you have an opinion on
>> https://gitlab.com/qemu-project/qemu/-/issues/3297 ?
>> Our Xilinx AXI ethernet device model lets software write to
>> the PHY registers for the PHY ID, and it's not clear to me
>> whether these registers are supposed to be read-only or not.
>>
>>
> Yes, they should be read-only, there's probably more registers and fields
> that have the wrong access restrictions as well. The PHY model is super
> simple, created just to get guests to not get stuck on boot or fail to use
> the PHY...
>
> IIRC, there's been several attempts on list to create a better MDIO/PHY
> interface with shared PHY models but never got merged.
>
> Cheers,
> Edgar
>

For example:
https://patchew.org/QEMU/20170922171323.10348-1-f4bug@amsat.org/

Patchew 2.1-devel-ea86937

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