The new CADENCE UART driver in upstream kernel access BXRS register
This patch adds BXRS (RX FIFO byte status register) or there would be
kernel panic if user are using the new CADENCE UART driver
Signed-off-by: Kuan-Jui Chiu <kchiu@axiado.com>
---
hw/char/cadence_uart.c | 2 ++
include/hw/char/cadence_uart.h | 2 +-
2 files changed, 3 insertions(+), 1 deletion(-)
diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c
index eff6a3c4d1..f57cad57a8 100644
--- a/hw/char/cadence_uart.c
+++ b/hw/char/cadence_uart.c
@@ -120,6 +120,7 @@
#define R_PMIN (0x3C/4)
#define R_PWID (0x40/4)
#define R_TTRIG (0x44/4)
+#define R_RXBS (0x48/4)
static void uart_update_status(CadenceUARTState *s)
@@ -523,6 +524,7 @@ static void cadence_uart_reset_init(Object *obj, ResetType type)
s->r[R_BRGR] = 0x0000028B;
s->r[R_BDIV] = 0x0000000F;
s->r[R_TTRIG] = 0x00000020;
+ s->r[R_RXBS] = 0;
}
static void cadence_uart_reset_hold(Object *obj, ResetType type)
diff --git a/include/hw/char/cadence_uart.h b/include/hw/char/cadence_uart.h
index 751a751248..0f97e19112 100644
--- a/include/hw/char/cadence_uart.h
+++ b/include/hw/char/cadence_uart.h
@@ -29,7 +29,7 @@
#define CADENCE_UART_RX_FIFO_SIZE 16
#define CADENCE_UART_TX_FIFO_SIZE 16
-#define CADENCE_UART_R_MAX (0x48/4)
+#define CADENCE_UART_R_MAX (0x4C/4)
#define TYPE_CADENCE_UART "cadence_uart"
OBJECT_DECLARE_SIMPLE_TYPE(CadenceUARTState, CADENCE_UART)
--
2.34.1