This commit removes TARGET_INSN_START_EXTRA_WORDS and force all arch to
call the same version of tcg_gen_insn_start, with additional 0 arguments
if needed. Since all arch have a single call site (in translate.c), this
is as good documentation as having a single define.
The notable exception is target/arm, which has two different translate
files for 32/64 bits. Since it's the only one, we accept to have two
call sites for this.
As well, we update parameter type to use uint64_t instead of
target_ulong, so it can be called from common code.
Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
include/tcg/tcg-op-common.h | 8 ++++++++
include/tcg/tcg-op.h | 29 -----------------------------
target/alpha/cpu-param.h | 2 --
target/arm/cpu-param.h | 7 -------
target/avr/cpu-param.h | 2 --
target/hexagon/cpu-param.h | 2 --
target/hppa/cpu-param.h | 2 --
target/i386/cpu-param.h | 2 --
target/loongarch/cpu-param.h | 2 --
target/m68k/cpu-param.h | 2 --
target/microblaze/cpu-param.h | 2 --
target/mips/cpu-param.h | 2 --
target/or1k/cpu-param.h | 2 --
target/ppc/cpu-param.h | 2 --
target/riscv/cpu-param.h | 7 -------
target/rx/cpu-param.h | 2 --
target/s390x/cpu-param.h | 2 --
target/sh4/cpu-param.h | 2 --
target/sparc/cpu-param.h | 2 --
target/tricore/cpu-param.h | 2 --
target/xtensa/cpu-param.h | 2 --
target/alpha/translate.c | 4 ++--
target/avr/translate.c | 2 +-
target/hexagon/translate.c | 2 +-
target/i386/tcg/translate.c | 2 +-
target/loongarch/tcg/translate.c | 2 +-
target/m68k/translate.c | 2 +-
target/microblaze/translate.c | 2 +-
target/or1k/translate.c | 2 +-
target/ppc/translate.c | 2 +-
target/rx/translate.c | 2 +-
target/sh4/translate.c | 4 ++--
target/sparc/translate.c | 2 +-
target/tricore/translate.c | 2 +-
target/xtensa/translate.c | 2 +-
35 files changed, 24 insertions(+), 93 deletions(-)
diff --git a/include/tcg/tcg-op-common.h b/include/tcg/tcg-op-common.h
index f752ef440b2..e02f209c093 100644
--- a/include/tcg/tcg-op-common.h
+++ b/include/tcg/tcg-op-common.h
@@ -30,6 +30,14 @@ TCGv_i64 tcg_global_mem_new_i64(TCGv_ptr reg, intptr_t off, const char *name);
TCGv_ptr tcg_global_mem_new_ptr(TCGv_ptr reg, intptr_t off, const char *name);
/* Generic ops. */
+static inline void tcg_gen_insn_start(uint64_t pc, uint64_t a1,
+ uint64_t a2)
+{
+ TCGOp *op = tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS);
+ tcg_set_insn_start_param(op, 0, pc);
+ tcg_set_insn_start_param(op, 1, a1);
+ tcg_set_insn_start_param(op, 2, a2);
+}
void gen_set_label(TCGLabel *l);
void tcg_gen_br(TCGLabel *l);
diff --git a/include/tcg/tcg-op.h b/include/tcg/tcg-op.h
index ee379994e76..7024be938e6 100644
--- a/include/tcg/tcg-op.h
+++ b/include/tcg/tcg-op.h
@@ -28,35 +28,6 @@
# error Mismatch with insn-start-words.h
#endif
-#if TARGET_INSN_START_EXTRA_WORDS == 0
-static inline void tcg_gen_insn_start(target_ulong pc)
-{
- TCGOp *op = tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS);
- tcg_set_insn_start_param(op, 0, pc);
- tcg_set_insn_start_param(op, 1, 0);
- tcg_set_insn_start_param(op, 2, 0);
-}
-#elif TARGET_INSN_START_EXTRA_WORDS == 1
-static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1)
-{
- TCGOp *op = tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS);
- tcg_set_insn_start_param(op, 0, pc);
- tcg_set_insn_start_param(op, 1, a1);
- tcg_set_insn_start_param(op, 2, 0);
-}
-#elif TARGET_INSN_START_EXTRA_WORDS == 2
-static inline void tcg_gen_insn_start(target_ulong pc, target_ulong a1,
- target_ulong a2)
-{
- TCGOp *op = tcg_emit_op(INDEX_op_insn_start, INSN_START_WORDS);
- tcg_set_insn_start_param(op, 0, pc);
- tcg_set_insn_start_param(op, 1, a1);
- tcg_set_insn_start_param(op, 2, a2);
-}
-#else
-#error Unhandled TARGET_INSN_START_EXTRA_WORDS value
-#endif
-
#if TARGET_LONG_BITS == 32
typedef TCGv_i32 TCGv;
#define tcg_temp_new() tcg_temp_new_i32()
diff --git a/target/alpha/cpu-param.h b/target/alpha/cpu-param.h
index a799f42db31..c9da620ab3e 100644
--- a/target/alpha/cpu-param.h
+++ b/target/alpha/cpu-param.h
@@ -24,6 +24,4 @@
# define TARGET_VIRT_ADDR_SPACE_BITS (30 + TARGET_PAGE_BITS)
#endif
-#define TARGET_INSN_START_EXTRA_WORDS 0
-
#endif
diff --git a/target/arm/cpu-param.h b/target/arm/cpu-param.h
index 8b46c7c5708..7de0099cbfa 100644
--- a/target/arm/cpu-param.h
+++ b/target/arm/cpu-param.h
@@ -32,11 +32,4 @@
# define TARGET_PAGE_BITS_LEGACY 10
#endif /* !CONFIG_USER_ONLY */
-/*
- * ARM-specific extra insn start words:
- * 1: Conditional execution bits
- * 2: Partial exception syndrome for data aborts
- */
-#define TARGET_INSN_START_EXTRA_WORDS 2
-
#endif
diff --git a/target/avr/cpu-param.h b/target/avr/cpu-param.h
index f74bfc25804..ea7887919a7 100644
--- a/target/avr/cpu-param.h
+++ b/target/avr/cpu-param.h
@@ -25,6 +25,4 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 24
#define TARGET_VIRT_ADDR_SPACE_BITS 24
-#define TARGET_INSN_START_EXTRA_WORDS 0
-
#endif
diff --git a/target/hexagon/cpu-param.h b/target/hexagon/cpu-param.h
index 635d509e743..45ee7b46409 100644
--- a/target/hexagon/cpu-param.h
+++ b/target/hexagon/cpu-param.h
@@ -23,6 +23,4 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 36
#define TARGET_VIRT_ADDR_SPACE_BITS 32
-#define TARGET_INSN_START_EXTRA_WORDS 0
-
#endif
diff --git a/target/hppa/cpu-param.h b/target/hppa/cpu-param.h
index 9bf7ac76d0c..e0b2c7c9157 100644
--- a/target/hppa/cpu-param.h
+++ b/target/hppa/cpu-param.h
@@ -19,6 +19,4 @@
#define TARGET_PAGE_BITS 12
-#define TARGET_INSN_START_EXTRA_WORDS 2
-
#endif
diff --git a/target/i386/cpu-param.h b/target/i386/cpu-param.h
index ebb844bcc83..909bc027923 100644
--- a/target/i386/cpu-param.h
+++ b/target/i386/cpu-param.h
@@ -22,6 +22,4 @@
#endif
#define TARGET_PAGE_BITS 12
-#define TARGET_INSN_START_EXTRA_WORDS 1
-
#endif
diff --git a/target/loongarch/cpu-param.h b/target/loongarch/cpu-param.h
index 58cc45a377e..071567712b3 100644
--- a/target/loongarch/cpu-param.h
+++ b/target/loongarch/cpu-param.h
@@ -13,6 +13,4 @@
#define TARGET_PAGE_BITS 12
-#define TARGET_INSN_START_EXTRA_WORDS 0
-
#endif
diff --git a/target/m68k/cpu-param.h b/target/m68k/cpu-param.h
index 256a2b5f8b2..7afbf6d302d 100644
--- a/target/m68k/cpu-param.h
+++ b/target/m68k/cpu-param.h
@@ -17,6 +17,4 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
-#define TARGET_INSN_START_EXTRA_WORDS 1
-
#endif
diff --git a/target/microblaze/cpu-param.h b/target/microblaze/cpu-param.h
index e0a37945136..6a0714bb3d7 100644
--- a/target/microblaze/cpu-param.h
+++ b/target/microblaze/cpu-param.h
@@ -27,6 +27,4 @@
/* FIXME: MB uses variable pages down to 1K but linux only uses 4k. */
#define TARGET_PAGE_BITS 12
-#define TARGET_INSN_START_EXTRA_WORDS 1
-
#endif
diff --git a/target/mips/cpu-param.h b/target/mips/cpu-param.h
index 58f450827f7..a71e7383d24 100644
--- a/target/mips/cpu-param.h
+++ b/target/mips/cpu-param.h
@@ -20,6 +20,4 @@
#endif
#define TARGET_PAGE_BITS 12
-#define TARGET_INSN_START_EXTRA_WORDS 2
-
#endif
diff --git a/target/or1k/cpu-param.h b/target/or1k/cpu-param.h
index b4f57bbe692..3011bf5fcca 100644
--- a/target/or1k/cpu-param.h
+++ b/target/or1k/cpu-param.h
@@ -12,6 +12,4 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
-#define TARGET_INSN_START_EXTRA_WORDS 1
-
#endif
diff --git a/target/ppc/cpu-param.h b/target/ppc/cpu-param.h
index e4ed9080ee9..ca7602d8983 100644
--- a/target/ppc/cpu-param.h
+++ b/target/ppc/cpu-param.h
@@ -37,6 +37,4 @@
# define TARGET_PAGE_BITS 12
#endif
-#define TARGET_INSN_START_EXTRA_WORDS 0
-
#endif
diff --git a/target/riscv/cpu-param.h b/target/riscv/cpu-param.h
index cfdc67c258c..039e877891a 100644
--- a/target/riscv/cpu-param.h
+++ b/target/riscv/cpu-param.h
@@ -17,13 +17,6 @@
#endif
#define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
-/*
- * RISC-V-specific extra insn start words:
- * 1: Original instruction opcode
- * 2: more information about instruction
- */
-#define TARGET_INSN_START_EXTRA_WORDS 2
-
/*
* The current MMU Modes are:
* - U mode 0b000
diff --git a/target/rx/cpu-param.h b/target/rx/cpu-param.h
index 84934f3bcaf..ef1970a09e9 100644
--- a/target/rx/cpu-param.h
+++ b/target/rx/cpu-param.h
@@ -24,6 +24,4 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
-#define TARGET_INSN_START_EXTRA_WORDS 0
-
#endif
diff --git a/target/s390x/cpu-param.h b/target/s390x/cpu-param.h
index abfae3bedfb..a5f798eeae7 100644
--- a/target/s390x/cpu-param.h
+++ b/target/s390x/cpu-param.h
@@ -12,6 +12,4 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 64
#define TARGET_VIRT_ADDR_SPACE_BITS 64
-#define TARGET_INSN_START_EXTRA_WORDS 2
-
#endif
diff --git a/target/sh4/cpu-param.h b/target/sh4/cpu-param.h
index f328715ee86..2b6e11dd0ac 100644
--- a/target/sh4/cpu-param.h
+++ b/target/sh4/cpu-param.h
@@ -16,6 +16,4 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
-#define TARGET_INSN_START_EXTRA_WORDS 1
-
#endif
diff --git a/target/sparc/cpu-param.h b/target/sparc/cpu-param.h
index 45eea9d6bac..6e8e2a51469 100644
--- a/target/sparc/cpu-param.h
+++ b/target/sparc/cpu-param.h
@@ -21,6 +21,4 @@
# define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
-#define TARGET_INSN_START_EXTRA_WORDS 1
-
#endif
diff --git a/target/tricore/cpu-param.h b/target/tricore/cpu-param.h
index eb33a67c419..790242ef3d2 100644
--- a/target/tricore/cpu-param.h
+++ b/target/tricore/cpu-param.h
@@ -12,6 +12,4 @@
#define TARGET_PHYS_ADDR_SPACE_BITS 32
#define TARGET_VIRT_ADDR_SPACE_BITS 32
-#define TARGET_INSN_START_EXTRA_WORDS 0
-
#endif
diff --git a/target/xtensa/cpu-param.h b/target/xtensa/cpu-param.h
index 7a0c22c9005..06d85218b84 100644
--- a/target/xtensa/cpu-param.h
+++ b/target/xtensa/cpu-param.h
@@ -16,6 +16,4 @@
#define TARGET_VIRT_ADDR_SPACE_BITS 32
#endif
-#define TARGET_INSN_START_EXTRA_WORDS 0
-
#endif
diff --git a/target/alpha/translate.c b/target/alpha/translate.c
index 4442462891e..4d22d7d5a45 100644
--- a/target/alpha/translate.c
+++ b/target/alpha/translate.c
@@ -2899,9 +2899,9 @@ static void alpha_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
DisasContext *ctx = container_of(dcbase, DisasContext, base);
if (ctx->pcrel) {
- tcg_gen_insn_start(dcbase->pc_next & ~TARGET_PAGE_MASK);
+ tcg_gen_insn_start(dcbase->pc_next & ~TARGET_PAGE_MASK, 0, 0);
} else {
- tcg_gen_insn_start(dcbase->pc_next);
+ tcg_gen_insn_start(dcbase->pc_next, 0, 0);
}
}
diff --git a/target/avr/translate.c b/target/avr/translate.c
index 78ae83df219..649dd4b0112 100644
--- a/target/avr/translate.c
+++ b/target/avr/translate.c
@@ -2689,7 +2689,7 @@ static void avr_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- tcg_gen_insn_start(ctx->npc);
+ tcg_gen_insn_start(ctx->npc, 0, 0);
}
static void avr_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index e88e19cc1af..1c9ab29bd12 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -978,7 +978,7 @@ static void hexagon_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- tcg_gen_insn_start(ctx->base.pc_next);
+ tcg_gen_insn_start(ctx->base.pc_next, 0, 0);
}
static bool pkt_crosses_page(CPUHexagonState *env, DisasContext *ctx)
diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 7186517239c..14210d569f7 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -3501,7 +3501,7 @@ static void i386_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
if (tb_cflags(dcbase->tb) & CF_PCREL) {
pc_arg &= ~TARGET_PAGE_MASK;
}
- tcg_gen_insn_start(pc_arg, dc->cc_op);
+ tcg_gen_insn_start(pc_arg, dc->cc_op, 0);
}
static void i386_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
diff --git a/target/loongarch/tcg/translate.c b/target/loongarch/tcg/translate.c
index 30f375b33f0..b9ed13d19c6 100644
--- a/target/loongarch/tcg/translate.c
+++ b/target/loongarch/tcg/translate.c
@@ -159,7 +159,7 @@ static void loongarch_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- tcg_gen_insn_start(ctx->base.pc_next);
+ tcg_gen_insn_start(ctx->base.pc_next, 0, 0);
}
/*
diff --git a/target/m68k/translate.c b/target/m68k/translate.c
index a0309939012..abc1c79f3cd 100644
--- a/target/m68k/translate.c
+++ b/target/m68k/translate.c
@@ -6041,7 +6041,7 @@ static void m68k_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
static void m68k_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *dc = container_of(dcbase, DisasContext, base);
- tcg_gen_insn_start(dc->base.pc_next, dc->cc_op);
+ tcg_gen_insn_start(dc->base.pc_next, dc->cc_op, 0);
}
static void m68k_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c
index 0be3c98dc17..2af67beecec 100644
--- a/target/microblaze/translate.c
+++ b/target/microblaze/translate.c
@@ -1630,7 +1630,7 @@ static void mb_tr_insn_start(DisasContextBase *dcb, CPUState *cs)
{
DisasContext *dc = container_of(dcb, DisasContext, base);
- tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK);
+ tcg_gen_insn_start(dc->base.pc_next, dc->tb_flags & ~MSR_TB_MASK, 0);
}
static void mb_tr_translate_insn(DisasContextBase *dcb, CPUState *cs)
diff --git a/target/or1k/translate.c b/target/or1k/translate.c
index ce2dc466dc7..de81dc6ef8d 100644
--- a/target/or1k/translate.c
+++ b/target/or1k/translate.c
@@ -1552,7 +1552,7 @@ static void openrisc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
DisasContext *dc = container_of(dcbase, DisasContext, base);
tcg_gen_insn_start(dc->base.pc_next, (dc->delayed_branch ? 1 : 0)
- | (dc->base.num_insns > 1 ? 2 : 0));
+ | (dc->base.num_insns > 1 ? 2 : 0), 0);
}
static void openrisc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
diff --git a/target/ppc/translate.c b/target/ppc/translate.c
index e9acfa239ec..a09a6df93fd 100644
--- a/target/ppc/translate.c
+++ b/target/ppc/translate.c
@@ -6575,7 +6575,7 @@ static void ppc_tr_tb_start(DisasContextBase *db, CPUState *cs)
static void ppc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
{
- tcg_gen_insn_start(dcbase->pc_next);
+ tcg_gen_insn_start(dcbase->pc_next, 0, 0);
}
static bool is_prefix_insn(DisasContext *ctx, uint32_t insn)
diff --git a/target/rx/translate.c b/target/rx/translate.c
index 26d41548294..a245b9db8fe 100644
--- a/target/rx/translate.c
+++ b/target/rx/translate.c
@@ -2217,7 +2217,7 @@ static void rx_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- tcg_gen_insn_start(ctx->base.pc_next);
+ tcg_gen_insn_start(ctx->base.pc_next, 0, 0);
}
static void rx_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
diff --git a/target/sh4/translate.c b/target/sh4/translate.c
index b3ae0a3814c..b1057727c55 100644
--- a/target/sh4/translate.c
+++ b/target/sh4/translate.c
@@ -2181,7 +2181,7 @@ static void decode_gusa(DisasContext *ctx, CPUSH4State *env)
* tb->icount * insn_start.
*/
for (i = 1; i < max_insns; ++i) {
- tcg_gen_insn_start(pc + i * 2, ctx->envflags);
+ tcg_gen_insn_start(pc + i * 2, ctx->envflags, 0);
ctx->base.insn_start = tcg_last_op();
}
}
@@ -2241,7 +2241,7 @@ static void sh4_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags);
+ tcg_gen_insn_start(ctx->base.pc_next, ctx->envflags, 0);
}
static void sh4_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
diff --git a/target/sparc/translate.c b/target/sparc/translate.c
index 57b50ff8b9a..7e8558dbbd8 100644
--- a/target/sparc/translate.c
+++ b/target/sparc/translate.c
@@ -5735,7 +5735,7 @@ static void sparc_tr_insn_start(DisasContextBase *dcbase, CPUState *cs)
g_assert_not_reached();
}
}
- tcg_gen_insn_start(dc->pc, npc);
+ tcg_gen_insn_start(dc->pc, npc, 0);
}
static void sparc_tr_translate_insn(DisasContextBase *dcbase, CPUState *cs)
diff --git a/target/tricore/translate.c b/target/tricore/translate.c
index 18d8726af6d..0eaf7a82f87 100644
--- a/target/tricore/translate.c
+++ b/target/tricore/translate.c
@@ -8410,7 +8410,7 @@ static void tricore_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
{
DisasContext *ctx = container_of(dcbase, DisasContext, base);
- tcg_gen_insn_start(ctx->base.pc_next);
+ tcg_gen_insn_start(ctx->base.pc_next, 0, 0);
}
static bool insn_crosses_page(DisasContext *ctx, CPUTriCoreState *env)
diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
index bb8d2ed86cf..5e3707d3fdf 100644
--- a/target/xtensa/translate.c
+++ b/target/xtensa/translate.c
@@ -1159,7 +1159,7 @@ static void xtensa_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
static void xtensa_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
{
- tcg_gen_insn_start(dcbase->pc_next);
+ tcg_gen_insn_start(dcbase->pc_next, 0, 0);
}
static void xtensa_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu)
--
2.47.3On 10/2/26 21:15, Pierrick Bouvier wrote:
> This commit removes TARGET_INSN_START_EXTRA_WORDS and force all arch to
> call the same version of tcg_gen_insn_start, with additional 0 arguments
> if needed. Since all arch have a single call site (in translate.c), this
> is as good documentation as having a single define.
>
> The notable exception is target/arm, which has two different translate
> files for 32/64 bits. Since it's the only one, we accept to have two
> call sites for this.
>
> As well, we update parameter type to use uint64_t instead of
> target_ulong, so it can be called from common code.
>
> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> ---
> include/tcg/tcg-op-common.h | 8 ++++++++
> include/tcg/tcg-op.h | 29 -----------------------------
> target/alpha/cpu-param.h | 2 --
> target/arm/cpu-param.h | 7 -------
> target/avr/cpu-param.h | 2 --
> target/hexagon/cpu-param.h | 2 --
> target/hppa/cpu-param.h | 2 --
> target/i386/cpu-param.h | 2 --
> target/loongarch/cpu-param.h | 2 --
> target/m68k/cpu-param.h | 2 --
> target/microblaze/cpu-param.h | 2 --
> target/mips/cpu-param.h | 2 --
> target/or1k/cpu-param.h | 2 --
> target/ppc/cpu-param.h | 2 --
> target/riscv/cpu-param.h | 7 -------
> target/rx/cpu-param.h | 2 --
> target/s390x/cpu-param.h | 2 --
> target/sh4/cpu-param.h | 2 --
> target/sparc/cpu-param.h | 2 --
> target/tricore/cpu-param.h | 2 --
> target/xtensa/cpu-param.h | 2 --
> target/alpha/translate.c | 4 ++--
> target/avr/translate.c | 2 +-
> target/hexagon/translate.c | 2 +-
> target/i386/tcg/translate.c | 2 +-
> target/loongarch/tcg/translate.c | 2 +-
> target/m68k/translate.c | 2 +-
> target/microblaze/translate.c | 2 +-
> target/or1k/translate.c | 2 +-
> target/ppc/translate.c | 2 +-
> target/rx/translate.c | 2 +-
> target/sh4/translate.c | 4 ++--
> target/sparc/translate.c | 2 +-
> target/tricore/translate.c | 2 +-
> target/xtensa/translate.c | 2 +-
> 35 files changed, 24 insertions(+), 93 deletions(-)
> diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c
> index bb8d2ed86cf..5e3707d3fdf 100644
> --- a/target/xtensa/translate.c
> +++ b/target/xtensa/translate.c
> @@ -1159,7 +1159,7 @@ static void xtensa_tr_tb_start(DisasContextBase *dcbase, CPUState *cpu)
>
> static void xtensa_tr_insn_start(DisasContextBase *dcbase, CPUState *cpu)
> {
> - tcg_gen_insn_start(dcbase->pc_next);
> + tcg_gen_insn_start(dcbase->pc_next, 0, 0);
If documentation is a concern, we could define INSN_START_DUMMY = 0 and
use it here.
> }
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
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