This patchset tries to address a discrepancy between the C3700 machine
in QEMU/SeaBIOS and the documentation (chapter 5)

  http://ftp.parisc-linux.org/docs/whitepapers/PA-8700wp.pdf

where 40 bits of physical address space are used in SeaBISO compared
to the 44 bits specified in the documentation.

A PA-8600 CPU with 40 bits of physical address space is added along with
a C3600 machine using it by default.  AFAICT there are no major
differences from QEMUs side between the PA-8600 and 8700 aside from the
physical address space size.  The PA-8700 machine can then be
moved to using 44 bits.  To account for the discrepancy with SeaBIOS, the
functional tests now run a C3700 but with a PA-8600 CPU.

CPU model definitions now inherit from a TYPE_HPPA_CPU base class and
use a HPPACPUDef sturct to provide model specifics, similar to the SPARC
and RISCV targets.  This hopefully makes it easier to add other models,
such as the 8800/8900.

Based on:
  PATCH v4 0/8] single-binary: Drop TARGET_PHYS_ADDR_SPACE_BITS
  (20260210-phys_addr-v4-0-725a589e83c8@rev.ng)

Signed-off-by: Anton Johansson <anjo@rev.ng>
---
Changes in v2:
- Missed a reference to the old "hppa" CPU model, updated to
  "pa-7300lc".
- Link to v1: https://lore.kernel.org/qemu-devel/20260210-hppa-c3600-v1-0-a17ec58f053f@rev.ng

---
Anton Johansson (4):
      hppa: Prepare for additional CPU models
      hppa: Introduce HPPACPUDef
      hppa: Get physical address space bits from CPUHPPADef
      hppa: Add C3600 machine with PA-8600 CPU

 target/hppa/cpu-qom.h                 |  8 ++++-
 target/hppa/cpu.h                     | 35 ++++++++++++++++----
 hw/hppa/machine.c                     | 62 +++++++++++++++++++++++++++--------
 hw/pci-host/astro.c                   |  2 +-
 linux-user/hppa/elfload.c             |  2 +-
 target/hppa/cpu.c                     | 52 ++++++++++++++++++++++-------
 target/hppa/mem_helper.c              | 40 +++++++---------------
 tests/qtest/machine-none-test.c       |  2 +-
 tests/functional/hppa/test_seabios.py |  3 ++
 9 files changed, 141 insertions(+), 65 deletions(-)

On 2/10/26 17:37, Anton Johansson via qemu development wrote:
> This patchset tries to address a discrepancy between the C3700 machine
> in QEMU/SeaBIOS and the documentation (chapter 5)
> 
>    http://ftp.parisc-linux.org/docs/whitepapers/PA-8700wp.pdf
> 
> where 40 bits of physical address space are used in SeaBISO compared

SeaBIOS (typo)

> to the 44 bits specified in the documentation.
> 
> A PA-8600 CPU with 40 bits of physical address space is added along with
> a C3600 machine using it by default.  AFAICT there are no major
> differences from QEMUs side between the PA-8600 and 8700 aside from the
> physical address space size.  The PA-8700 machine can then be
> moved to using 44 bits.  To account for the discrepancy with SeaBIOS, the
> functional tests now run a C3700 but with a PA-8600 CPU.
> 
> CPU model definitions now inherit from a TYPE_HPPA_CPU base class and
> use a HPPACPUDef sturct to provide model specifics, similar to the SPARC
> and RISCV targets.  This hopefully makes it easier to add other models,
> such as the 8800/8900.
> 
> Based on:
>    PATCH v4 0/8] single-binary: Drop TARGET_PHYS_ADDR_SPACE_BITS
>    (20260210-phys_addr-v4-0-725a589e83c8@rev.ng)
> 
> Signed-off-by: Anton Johansson <anjo@rev.ng>

I like your patchset.
I'm just wondering if we should merge it with my upcoming new SeaBIOS,
which adds support for an A400 machine (with a PA8500 CPU).
So, instead of adding a C3600 machine, we could add the A400 which
has 40-bit physical addresss space too.
See:
https://github.com/hdeller/seabios-hppa/branches -> devel-v22 branch
and
https://github.com/hdeller/qemu-hppa/commit/1c969c925fb76236e76b09e011f07766ab4441cb

In addition, I wonder what's necessary to change in SeaBIOS to fully
support the 40 and/or 44-bit case. It's easy to hand over the bits to
SeaBIOS, so SeaBIOS could do the right thing.

Helge