On Thu, Feb 05, 2026 at 12:44:02AM +0800, Chao Liu wrote:
> On Wed, Feb 04, 2026 at 01:17:55PM +0800, Max Chou wrote:
> > This patch adds support to disassemble Zvfofp4min instructions.
> >
> > Signed-off-by: Max Chou <max.chou@sifive.com>
> > ---
> > disas/riscv.c | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/disas/riscv.c b/disas/riscv.c
> > index daffe9917f..9abf86f2d7 100644
> > --- a/disas/riscv.c
> > +++ b/disas/riscv.c
> > @@ -987,6 +987,7 @@ typedef enum {
> > rv_op_vfncvtbf16_sat_f_f_w = 956,
> > rv_op_vfncvt_f_f_q = 957,
> > rv_op_vfncvt_sat_f_f_q = 958,
> > + rv_op_vfext_vf2 = 959,
> > } rv_op;
> >
> > /* register names */
> > @@ -2260,6 +2261,7 @@ const rv_opcode_data rvi_opcode_data[] = {
> > { "vfncvtbf16.sat.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> > { "vfncvt.f.f.q", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> > { "vfncvt.sat.f.f.q", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> > + { "vfext.vf2", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> > };
> >
> > /* CSR names */
> > @@ -3715,6 +3717,7 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> > case 12: op = rv_op_vclz_v; break;
> > case 13: op = rv_op_vctz_v; break;
> > case 14: op = rv_op_vcpop_v; break;
> > + case 22: op = rv_op_vfext_vf2; break;
> checkpatch reports:
> ERROR: trailing statements should be on next line
>
> But this should be on next line" can be ignored (Patch 9 too). The existing disas/riscv.c file
Correction: This is similar to the case in Patch 14. We can keep the current code style.
Thanks,
Chao
> consistently uses the single-line format:
> case X: op = rv_op_xxx; break;
>
> Maintaining consistency with the existing file style takes precedence here.
>
> Other, LGTM.
>
> Reviewed-by: Chao Liu <chao.liu.zevorn@gmail.com>
>
> Thanks,
> Chao
> > }
> > break;
> > case 20:
> > --
> > 2.52.0
> >
> >