On Wed, Feb 04, 2026 at 01:17:50PM +0800, Max Chou wrote:
> This patch adds support to disassemble Zvfofp8min instructions.
>
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
> disas/riscv.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/disas/riscv.c b/disas/riscv.c
> index 85cd2a9c2a..daffe9917f 100644
> --- a/disas/riscv.c
> +++ b/disas/riscv.c
> @@ -984,6 +984,9 @@ typedef enum {
> rv_op_ssamoswap_d = 953,
> rv_op_c_sspush = 954,
> rv_op_c_sspopchk = 955,
> + rv_op_vfncvtbf16_sat_f_f_w = 956,
> + rv_op_vfncvt_f_f_q = 957,
> + rv_op_vfncvt_sat_f_f_q = 958,
> } rv_op;
>
> /* register names */
> @@ -2254,6 +2257,9 @@ const rv_opcode_data rvi_opcode_data[] = {
> rv_op_sspush, 0 },
> { "c.sspopchk", rv_codec_cmop_ss, rv_fmt_rs1, NULL, rv_op_sspopchk,
> rv_op_sspopchk, 0 },
> + { "vfncvtbf16.sat.f.f.w", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> + { "vfncvt.f.f.q", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> + { "vfncvt.sat.f.f.q", rv_codec_v_r, rv_fmt_vd_vs2_vm, NULL, 0, 0, 0 },
> };
>
> /* CSR names */
> @@ -3630,7 +3636,10 @@ static void decode_inst_opcode(rv_decode *dec, rv_isa isa)
> case 21: op = rv_op_vfncvt_rod_f_f_w; break;
> case 22: op = rv_op_vfncvt_rtz_xu_f_w; break;
> case 23: op = rv_op_vfncvt_rtz_x_f_w; break;
> + case 25: op = rv_op_vfncvt_f_f_q; break;
> + case 27: op = rv_op_vfncvt_sat_f_f_q; break;
> case 29: op = rv_op_vfncvtbf16_f_f_w; break;
> + case 31: op = rv_op_vfncvtbf16_sat_f_f_w; break;
checkpatch reports:
ERROR: trailing statements should be on next line
The QEMU coding style requires that the statement after 'case' should be
on a new line. Please reformat as:
case 25:
op = rv_op_vfncvt_f_f_q;
break;
case 27:
op = rv_op_vfncvt_sat_f_f_q;
break;
case 31:
op = rv_op_vfncvtbf16_sat_f_f_w;
break;
Thanks,
Chao
> }
> break;
> case 19:
> --
> 2.52.0
>
>