On 2/3/26 05:08, Jamin Lin via qemu development wrote:
> EHCI3 and EHCI4 were missing entries in aspeed_soc_ast2700a1_irqmap,
> so their source IRQs were never routed through the INTC OR-gates.
>
> As a result, EHCI3/4 interrupts were not propagated to the GIC,
> causing incorrect interrupt behavior for these controllers.
>
> Add EHCI3 and EHCI4 to the IRQ map and route them to the same INTC
> group as other shared peripherals, ensuring their interrupts are
> properly connected to the GIC.
>
> Signed-off-by: Jamin Lin <jamin_lin@aspeedtech.com>
> Fixes: ba27ba302a264117c8b8427f944ced1bed17c438 ("hw/arm: ast27x0: Wire up EHCI controllers")
> Reviewed-by: Cédric Le Goater <clg@redhat.com>
This looks like a qemu-stable material (10.1.x, 10.2.x).
Please let me know if it isn't.
Thanks,
/mjt
> ---
> hw/arm/aspeed_ast27x0.c | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/hw/arm/aspeed_ast27x0.c b/hw/arm/aspeed_ast27x0.c
> index d17f446661..e16183c3b3 100644
> --- a/hw/arm/aspeed_ast27x0.c
> +++ b/hw/arm/aspeed_ast27x0.c
> @@ -149,6 +149,8 @@ static const int aspeed_soc_ast2700a1_irqmap[] = {
> [ASPEED_DEV_ETH1] = 196,
> [ASPEED_DEV_ETH2] = 196,
> [ASPEED_DEV_ETH3] = 196,
> + [ASPEED_DEV_EHCI3] = 196,
> + [ASPEED_DEV_EHCI4] = 196,
> [ASPEED_DEV_PECI] = 197,
> [ASPEED_DEV_SDHCI] = 197,
> };