target/riscv: Inline cpu_ld[lq]_code() calls

[PATCH] target/riscv: Inline cpu_ld[lq]_code() calls

Posted by Philippe Mathieu-Daudé 4 days, 11 hours ago

In preparation of removing the cpu_ldl_code() and cpu_ldq_code()
wrappers, inline them.

Since RISC-V instructions are always stored in little-endian order
(see "Volume I: RISC-V Unprivileged ISA" document, chapter
'Instruction Encoding Spaces and Prefixes': "instruction fetch
in RISC-V is little-endian"), replace MO_TE -> MO_LE.

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/riscv/translate.c  | 3 ++-
 target/riscv/zce_helper.c | 8 ++++++--
 2 files changed, 8 insertions(+), 3 deletions(-)

diff --git a/target/riscv/translate.c b/target/riscv/translate.c
index d8261aeb662..cb4f4436018 100644
--- a/target/riscv/translate.c
+++ b/target/riscv/translate.c
@@ -1181,8 +1181,9 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
     DisasContext *ctx = container_of(dcbase, DisasContext, base);
     CPUState *cpu = ctx->cs;
     CPURISCVState *env = cpu_env(cpu);
+    MemOpIdx oi = make_memop_idx(MO_LEUL, cpu_mmu_index(cpu, true));
 
-    return cpu_ldl_code(env, pc);
+    return cpu_ldl_code_mmu(env, pc, oi, 0);
 }
 
 #define SS_MMU_INDEX(ctx) (ctx->mem_idx | MMU_IDX_SS_WRITE)
diff --git a/target/riscv/zce_helper.c b/target/riscv/zce_helper.c
index 55221f5f375..15bf0a99c8a 100644
--- a/target/riscv/zce_helper.c
+++ b/target/riscv/zce_helper.c
@@ -23,6 +23,8 @@
 
 target_ulong HELPER(cm_jalt)(CPURISCVState *env, uint32_t index)
 {
+    unsigned mmu_index = cpu_mmu_index(env_cpu(env), true);
+    MemOpIdx oi;
 
 #if !defined(CONFIG_USER_ONLY)
     RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT);
@@ -43,11 +45,13 @@ target_ulong HELPER(cm_jalt)(CPURISCVState *env, uint32_t index)
     }
 
     if (xlen == 32) {
+        oi = make_memop_idx(MO_LEUL, mmu_index);
         t0 = base + (index << 2);
-        target = cpu_ldl_code(env, t0);
+        target = cpu_ldl_code_mmu(env, t0, oi, 0);
     } else {
+        oi = make_memop_idx(MO_LEUQ, mmu_index);
         t0 = base + (index << 3);
-        target = cpu_ldq_code(env, t0);
+        target = cpu_ldq_code_mmu(env, t0, oi, 0);
     }
 
     return target & ~0x1;
-- 
2.52.0

Re: [PATCH] target/riscv: Inline cpu_ld[lq]_code() calls

Posted by Philippe Mathieu-Daudé 3 days, 17 hours ago

On 2/2/26 22:43, Philippe Mathieu-Daudé wrote:
> In preparation of removing the cpu_ldl_code() and cpu_ldq_code()
> wrappers, inline them.
> 
> Since RISC-V instructions are always stored in little-endian order
> (see "Volume I: RISC-V Unprivileged ISA" document, chapter
> 'Instruction Encoding Spaces and Prefixes': "instruction fetch
> in RISC-V is little-endian"), replace MO_TE -> MO_LE.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/riscv/translate.c  | 3 ++-
>   target/riscv/zce_helper.c | 8 ++++++--
>   2 files changed, 8 insertions(+), 3 deletions(-)

Patch queued, thanks.

Re: [PATCH] target/riscv: Inline cpu_ld[lq]_code() calls

Posted by Richard Henderson 4 days, 5 hours ago

On 2/3/26 07:43, Philippe Mathieu-Daudé wrote:
> In preparation of removing the cpu_ldl_code() and cpu_ldq_code()
> wrappers, inline them.
> 
> Since RISC-V instructions are always stored in little-endian order
> (see "Volume I: RISC-V Unprivileged ISA" document, chapter
> 'Instruction Encoding Spaces and Prefixes': "instruction fetch
> in RISC-V is little-endian"), replace MO_TE -> MO_LE.
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>   target/riscv/translate.c  | 3 ++-
>   target/riscv/zce_helper.c | 8 ++++++--
>   2 files changed, 8 insertions(+), 3 deletions(-)
> 
> diff --git a/target/riscv/translate.c b/target/riscv/translate.c
> index d8261aeb662..cb4f4436018 100644
> --- a/target/riscv/translate.c
> +++ b/target/riscv/translate.c
> @@ -1181,8 +1181,9 @@ static uint32_t opcode_at(DisasContextBase *dcbase, target_ulong pc)
>       DisasContext *ctx = container_of(dcbase, DisasContext, base);
>       CPUState *cpu = ctx->cs;
>       CPURISCVState *env = cpu_env(cpu);
> +    MemOpIdx oi = make_memop_idx(MO_LEUL, cpu_mmu_index(cpu, true));
>   
> -    return cpu_ldl_code(env, pc);
> +    return cpu_ldl_code_mmu(env, pc, oi, 0);
>   }
>   
>   #define SS_MMU_INDEX(ctx) (ctx->mem_idx | MMU_IDX_SS_WRITE)
> diff --git a/target/riscv/zce_helper.c b/target/riscv/zce_helper.c
> index 55221f5f375..15bf0a99c8a 100644
> --- a/target/riscv/zce_helper.c
> +++ b/target/riscv/zce_helper.c
> @@ -23,6 +23,8 @@
>   
>   target_ulong HELPER(cm_jalt)(CPURISCVState *env, uint32_t index)
>   {
> +    unsigned mmu_index = cpu_mmu_index(env_cpu(env), true);
> +    MemOpIdx oi;
>   
>   #if !defined(CONFIG_USER_ONLY)
>       RISCVException ret = smstateen_acc_ok(env, 0, SMSTATEEN0_JVT);
> @@ -43,11 +45,13 @@ target_ulong HELPER(cm_jalt)(CPURISCVState *env, uint32_t index)
>       }
>   
>       if (xlen == 32) {
> +        oi = make_memop_idx(MO_LEUL, mmu_index);
>           t0 = base + (index << 2);
> -        target = cpu_ldl_code(env, t0);
> +        target = cpu_ldl_code_mmu(env, t0, oi, 0);
>       } else {
> +        oi = make_memop_idx(MO_LEUQ, mmu_index);
>           t0 = base + (index << 3);
> -        target = cpu_ldq_code(env, t0);
> +        target = cpu_ldq_code_mmu(env, t0, oi, 0);
>       }
>   
>       return target & ~0x1;

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~