On 2/2/26 23:33, Peter Maydell wrote:
> The SVE RAX1 instruction is permitted in SME streaming mode starting
> from SME2p1. We forgot to allow this relaxation when we implemented
> SME2p1.
>
> Cc: qemu-stable@nongnu.org
> Fixes: 7b1613a1020d2 ("target/arm: Enable FEAT_SME2p1 on -cpu max")
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
> target/arm/tcg/translate-sve.c | 13 +++++++++++--
> 1 file changed, 11 insertions(+), 2 deletions(-)
>
> diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
> index 81f487152c..e853b4dd0a 100644
> --- a/target/arm/tcg/translate-sve.c
> +++ b/target/arm/tcg/translate-sve.c
> @@ -7803,8 +7803,17 @@ TRANS_FEAT_NONSTREAMING(SM4E, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
> TRANS_FEAT_NONSTREAMING(SM4EKEY, aa64_sve2_sm4, gen_gvec_ool_arg_zzz,
> gen_helper_crypto_sm4ekey, a, 0)
>
> -TRANS_FEAT_NONSTREAMING(RAX1, aa64_sve2_sha3, gen_gvec_fn_arg_zzz,
> - gen_gvec_rax1, a)
> +static bool trans_RAX1(DisasContext *s, arg_RAX1 *a)
> +{
> + if (!dc_isar_feature(aa64_sve2_sha3, s)) {
> + return false;
> + }
> + if (!dc_isar_feature(aa64_sme2p1, s)) {
> + /* SME2p1 adds this as valid in streaming SVE mode */
> + s->is_nonstreaming = true;
> + }
> + return gen_gvec_fn_arg_zzz(s, gen_gvec_rax1, a);
> +}
>
> TRANS_FEAT(FCVTNT_sh, aa64_sve2, gen_gvec_fpst_arg_zpz,
> gen_helper_sve2_fcvtnt_sh, a, 0, FPST_A64)
I wonder if we should update sme-fa64.decode instead of handling this per-insn?
Anyway,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~