Part of the logic inside do_trans_pmull() applies the aa64_sve
feature check for the non-128-bit-element versions of these insns
(PMULLB and PMULLT).  This is currently a redundant check because we
only invoke this function via the macro invocation
 TRANS_FEAT(..., aa64_sve2, do_trans_pmull, ...)
and it's actively wrong for an SME-only CPU, because these insns
are also available via SME. Remove the unnecessary logic.

Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
 target/arm/tcg/translate-sve.c | 2 --
 1 file changed, 2 deletions(-)

diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
index e853b4dd0a..fe59126d2b 100644
--- a/target/arm/tcg/translate-sve.c
+++ b/target/arm/tcg/translate-sve.c
@@ -6782,8 +6782,6 @@ static bool do_trans_pmull(DisasContext *s, arg_rrr_esz *a, bool sel)
             return false;
         }
         s->is_nonstreaming = true;
-    } else if (!dc_isar_feature(aa64_sve, s)) {
-        return false;
     }
     return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, sel);
 }
-- 
2.43.0

On 2/2/26 23:33, Peter Maydell wrote:
> Part of the logic inside do_trans_pmull() applies the aa64_sve
> feature check for the non-128-bit-element versions of these insns
> (PMULLB and PMULLT).  This is currently a redundant check because we
> only invoke this function via the macro invocation
>   TRANS_FEAT(..., aa64_sve2, do_trans_pmull, ...)
> and it's actively wrong for an SME-only CPU, because these insns
> are also available via SME. Remove the unnecessary logic.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>   target/arm/tcg/translate-sve.c | 2 --
>   1 file changed, 2 deletions(-)
> 
> diff --git a/target/arm/tcg/translate-sve.c b/target/arm/tcg/translate-sve.c
> index e853b4dd0a..fe59126d2b 100644
> --- a/target/arm/tcg/translate-sve.c
> +++ b/target/arm/tcg/translate-sve.c
> @@ -6782,8 +6782,6 @@ static bool do_trans_pmull(DisasContext *s, arg_rrr_esz *a, bool sel)
>               return false;
>           }
>           s->is_nonstreaming = true;
> -    } else if (!dc_isar_feature(aa64_sve, s)) {
> -        return false;
>       }
>       return gen_gvec_ool_arg_zzz(s, fns[a->esz], a, sel);
>   }


Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~