In commit f7767ca30179 ("target/arm: Disable SME if SVE is disabled")
we added code that forces SME to be disabled if SVE is disabled.
This was something we did in the run-up to a release to avoid an
assertion failure in smcr_write() if the user disabled SVE on the
'max' CPU without disabling SME also.
Now that we have corrected the code so that it doesn't assert
in an SME-without-SVE setup, we can let users select it.
This effectively reverts f7767ca30179.
Note that this now means that command lines like "-cpu max,sve=off"
which used to turn off SME and SVE will now give you a CPU with SME
but not SVE. This is permitted by our loose "max can always give you
extra stuff" rules, but may be unexpected to users. Mention this in
the CPU property documentation.
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
---
docs/system/arm/cpu-features.rst | 10 ++++++++--
target/arm/cpu.c | 10 ----------
2 files changed, 8 insertions(+), 12 deletions(-)
diff --git a/docs/system/arm/cpu-features.rst b/docs/system/arm/cpu-features.rst
index 37d5dfd15b..9d0c5731cc 100644
--- a/docs/system/arm/cpu-features.rst
+++ b/docs/system/arm/cpu-features.rst
@@ -318,12 +318,18 @@ SVE CPU Property Parsing Semantics
provided an error will be generated. To avoid this error, one must
enable at least one vector length prior to enabling SVE.
+ 10) Disabling SVE does not automatically disable SME. If you want to
+ disable both you must use ``sve=off,sme=off``. In particular,
+ for the ``max`` CPU, ``sve=off`` alone will give you a CPU with
+ SME only (and which therefore still has the SVE vector registers).
+ Most users will want to disable both at once.
+
SVE CPU Property Examples
-------------------------
- 1) Disable SVE::
+ 1) Disable SVE and SME::
- $ qemu-system-aarch64 -M virt -cpu max,sve=off
+ $ qemu-system-aarch64 -M virt -cpu max,sve=off,sme=off
2) Implicitly enable all vector lengths for the ``max`` CPU type::
diff --git a/target/arm/cpu.c b/target/arm/cpu.c
index 6e1cbf3d61..1cb30076ad 100644
--- a/target/arm/cpu.c
+++ b/target/arm/cpu.c
@@ -1571,16 +1571,6 @@ void arm_cpu_finalize_features(ARMCPU *cpu, Error **errp)
return;
}
- /*
- * FEAT_SME is not architecturally dependent on FEAT_SVE (unless
- * FEAT_SME_FA64 is present). However our implementation currently
- * assumes it, so if the user asked for sve=off then turn off SME also.
- * (KVM doesn't currently support SME at all.)
- */
- if (cpu_isar_feature(aa64_sme, cpu) && !cpu_isar_feature(aa64_sve, cpu)) {
- object_property_set_bool(OBJECT(cpu), "sme", false, &error_abort);
- }
-
arm_cpu_sme_finalize(cpu, &local_err);
if (local_err != NULL) {
error_propagate(errp, local_err);
--
2.43.0