These patches add support to TCG for a CPU with SME but not SVE.  We
originally prevented users from doing that in the run-up to a
release, in commit f7767ca30179 ("target/arm: Disable SME if SVE is
disabled") by forcing SME to off if SVE wasn't implemented.  This was
a simple way to avoid users hitting an assertion failure.

Changes since v1:
 * reorder patches to put the ones that affect SME+SVE
   CPUs and are worth backporting to stable first
 * change approach to fixing the smcr_write() assertion
 * fix a non-SME-aware assert in aarch64_sve_narrow_vq()
 * correct a bug in how we report the vector registers in
   the gdbstub: this fixes the problem where gdb hit an
   internal error when we emulate SME-only CPU
 * squash FEAT_SME_FA64 on SME-only CPUs

This has still not really had a great deal of testing, but
I think it's now good enough to remove the RFC tag.

thanks
-- PMM

Peter Maydell (6):
  target/arm: Account for SME in aarch64_sve_narrow_vq() assertion
  target/arm: Report correct vector width in gdbstub when SME present
  target/arm: Handle SME-only CPUs in sve_vqm1_for_el_sm()
  target/arm: Handle SME-without-SVE on change of EL
  target/arm: Squash FEAT_SME_FA64 if FEAT_SVE is not present
  target/arm: Permit configurations with SME but not SVE

 docs/system/arm/cpu-features.rst | 10 ++++++++--
 target/arm/cpu.c                 | 10 ----------
 target/arm/cpu64.c               |  5 +++++
 target/arm/gdbstub64.c           | 12 ++++++------
 target/arm/helper.c              | 14 ++++++++++----
 target/arm/internals.h           |  9 +++++++++
 6 files changed, 38 insertions(+), 22 deletions(-)

-- 
2.43.0