These patches add support to TCG for a CPU with SME but not SVE.  We
originally prevented users from doing that in the run-up to a
release, in commit f7767ca30179 ("target/arm: Disable SME if SVE is
disabled") by forcing SME to off if SVE wasn't implemented.  This was
a simple way to avoid users hitting an assertion failure.

I tracked down exactly why we were getting that assertion failure,
and fixed another "assumes SME implies SME" issue I spotted in the
code while I was auditing the various callers of
sve_vqm1_sve_for_el().  This lets us remove the hack we originally
put in.

This is an RFC because:
 * I tested that we can boot a kernel and it detects SME, but
   don't have an SME guest workload to hand that does much
   with registers, vector length, etc.
 * having "-cpu max,sve=off" now give you this oddball
   "SME only" config is perhaps surprising to users. We could
   perhaps flag this up in cpu-features.rst somewhere.
 * as noted in the other thread that adds hvf support for
   SME-only CPUs, it turns out that gdb will crash if you
   connect it to our debug stub in this config.

But I think the first two patches are worth getting reviewed
and into the tree even if we haven't figured out yet if we
want to hold off until we have an idea what to do about gdb.

Peter Maydell (3):
  target/arm: Make smcr_write() handle SME-without-SVE
  target/arm: Handle SME-without-SVE on change of EL
  target/arm: Permit configurations with SME but not SVE

 target/arm/cpu.c    | 10 ----------
 target/arm/helper.c | 23 +++++++++++++++--------
 2 files changed, 15 insertions(+), 18 deletions(-)

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2.43.0