This patchset adds support for the OCP (Open Compute Project) 8-bit and
4-bit floating-point formats, along with the RISC-V Zvfofp8min and
Zvfofp4min vector extensions that provide conversion operations for
these formats.
OCP Floating-Point Formats
* The OCP FP8 specification defines two 8-bit floating-point formats:
- E4M3: 4-bit exponent, 3-bit mantissa
* No infinity representation; only 0x7f and 0xff are NaN
- E5M2: 5-bit exponent, 2-bit mantissa
* IEEE-like format with infinity representation
* Multiple NaN encodings supported
* The OCP FP4 specification defines the E2M1 format:
- E2M1: 2-bit exponent, 1-bit mantissa
* No NaN representation
RISC-V ISA Extensions
* Zvfofp8min (Version 0.2.1):
The Zvfofp8min extension provides minimal vector conversion support
for OFP8 formats. It requires the Zve32f extension and leverages the
altfmt field in the VTYPE CSR (introduced by Zvfbfa) to select between
E4M3 (altfmt=0) and E5M2 (altfmt=1) formats.
- Canonical NaN for both E4M3 and E5M2 is 0x7f
- All NaNs are treated as quiet NaNs
Instructions added/extended:
- vfwcvtbf16.f.f.v: OFP8 to BF16 widening conversion
- vfncvtbf16.f.f.w: BF16 to OFP8 narrowing conversion
- vfncvtbf16.sat.f.f.w: BF16 to OFP8 with saturation (new)
- vfncvt.f.f.q: FP32 to OFP8 quad-narrowing conversion (new)
- vfncvt.sat.f.f.q: FP32 to OFP8 with saturation (new)
* Zvfofp4min (Version 0.1):
The Zvfofp4min extension provides minimal vector conversion support
for the OFP4 E2M1 format. It requires the Zve32f extension.
Instructions added:
- vfext.vf2: OFP4 E2M1 to OFP8 E4M3 widening conversion
Modifications
* Softfloat library:
- Refactored IEEE format NaN classification to share code (new in v2)
- New float8_e4m3 and float8_e5m2 types with NaN checking functions
- New float4_e2m1 type for OFP4 support
- Conversion functions: bfloat16/float32 <-> float8_e4m3/float8_e5m2
- Conversion function: float4_e2m1 -> float8_e4m3
- Implementation uses capability-based FloatFmt flags for format behavior
* RISC-V target:
- CPU configuration properties for Zvfofp8min and Zvfofp4min
- Extension implied rules (Zvfofp8min requires Zve32f and Zvfbfa)
- Vector helper functions for OFP8/OFP4 conversion instructions
- Disassembler support for new instructions
Changes in v2:
= Merged v1 patch 2 & 3 to v2 patch 3, v1 patch 4 & 5 to v2 patch 4
- Added new v2 patch 2 to refactor the IEEE format NaN classification
functions (float16, bfloat16, float32, float64) to use internal helper
functions, reducing code duplication and improving maintainability.
The OCP FP8 NaN classification functions follow the same pattern.
- Refactored softfloat implementation to use capability-based FloatFmt
flags (no_infinity, limited_nan, overflow_raises_invalid, normal_frac_max)
instead of monolithic flags
- Removed ocp_fp8e5m2_no_signal_nan and ocp_fp8_same_canonical_nan flags
from float_status; now using local float_status with no_signaling_nans
and default_nan_pattern for RISC-V Zvfofp8min instructions
- Rebased on latest riscv-to-apply.next with zvfbfa v3 patchset
References
* OCP FP8 specification:
https://www.opencompute.org/documents/ocp-8-bit-floating-point-specification-ofp8-revision-1-0-2023-12-01-pdf-1
* Zvfofp8min specification (v0.2.1 commit e1e20a7):
https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfofp8min.adoc
* Zvfofp4min specification (v0.1 commit e1e20a7):
https://github.com/aswaterman/riscv-misc/blob/main/isa/zvfofp4min.adoc
PS: This series depends on the Zvfbfa extension patchset which introduces:
- The altfmt field in VTYPE CSR
- BF16 vector operations infrastructure
- vfwcvtbf16.f.f.v and vfncvtbf16.f.f.w base instructions
v1: <20260108151650.16329-1-max.chou@sifive.com>
Based-on: 20260127014227.406653-1-max.chou@sifive.com
Max Chou (17):
target/riscv: rvv: Fix NOP_UU_B vs2 width
fpu/softfloat: Refactor IEEE format NaN classification to share code
fpu/softfloat: Support OCP(Open Compute Project) OFP8 data type
fpu/softfloat: Support OCP(Open Compute Project) OFP4 data type
target/riscv: Add cfg properity for Zvfofp8min extension
target/riscv: Add implied rules for Zvfofp8min extension
target/riscv: rvv: Make vfwcvtbf16.f.f.v support OFP8 to BF16
conversion for Zvfofp8min extension
target/riscv: rvv: Make vfncvtbf16.f.f.w support BF16 to OFP8
conversion for Zvfofp8min extension
target/riscv: rvv: Add vfncvtbf16.sat.f.f.w instruction for Zvfofp8min
extension
target/riscv: rvv: Add vfncvt.f.f.q and vfncvt.sat.f.f.q instructions
for Zvfofp8min extension
target/riscv: Expose Zvfofp8min properity
disas/riscv: Add support of Zvfofp8min extension
target/riscv: Add cfg properity for Zvfofp4min extension
target/riscv: Add implied rules for Zvfofp4min extension
target/riscv: rvv: Add vfext.vf2 instruction for Zvfofp4min extension
target/riscv: Expose Zvfofp4min properity
disas/riscv: Add support of Zvfofp4min extension
disas/riscv.c | 12 ++
fpu/softfloat-parts.c.inc | 159 ++++++++++++---
fpu/softfloat-specialize.c.inc | 227 ++++++++++++++-------
fpu/softfloat.c | 220 +++++++++++++++++++-
include/fpu/softfloat-types.h | 17 ++
include/fpu/softfloat.h | 124 +++++++++++
target/riscv/cpu.c | 32 ++-
target/riscv/cpu_cfg_fields.h.inc | 2 +
target/riscv/helper.h | 15 ++
target/riscv/insn32.decode | 8 +
target/riscv/insn_trans/trans_rvbf16.c.inc | 32 ++-
target/riscv/insn_trans/trans_rvofp4.c.inc | 44 ++++
target/riscv/insn_trans/trans_rvofp8.c.inc | 106 ++++++++++
target/riscv/insn_trans/trans_rvv.c.inc | 39 ++++
target/riscv/tcg/tcg-cpu.c | 10 +
target/riscv/translate.c | 2 +
target/riscv/vector_helper.c | 135 +++++++++++-
17 files changed, 1059 insertions(+), 125 deletions(-)
create mode 100644 target/riscv/insn_trans/trans_rvofp4.c.inc
create mode 100644 target/riscv/insn_trans/trans_rvofp8.c.inc
--
2.52.0