On 2026/1/26 18:43, Shameer Kolothum wrote:
> Refactor PCIe PASID capability initialization by moving the common
> register init into a new helper, pcie_pasid_common_init().
>
> Subsequent patch to synthesize a vPASID will make use of this
> helper.
>
> No functional change intended.
>
> Cc: Michael S. Tsirkin <mst@redhat.com>
> Reviewed-by: Jonathan Cameron <jonathan.cameron@huawei.com>
> Reviewed-by: Eric Auger <eric.auger@redhat.com>
> Reviewed-by: Michael S. Tsirkin <mst@redhat.com>
> Tested-by: Eric Auger <eric.auger@redhat.com>
> Tested-by: Zhangfei Gao <zhangfei.gao@linaro.org>
> Signed-off-by: Shameer Kolothum <skolothumtho@nvidia.com>
> ---
> hw/pci/pcie.c | 19 ++++++++++++-------
> include/hw/pci/pcie.h | 2 ++
> 2 files changed, 14 insertions(+), 7 deletions(-)
Reviewed-by: Yi Liu <yi.l.liu@intel.com>
> diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c
> index aa9024e532..c481c16c0f 100644
> --- a/hw/pci/pcie.c
> +++ b/hw/pci/pcie.c
> @@ -1284,18 +1284,13 @@ void pcie_acs_reset(PCIDevice *dev)
> }
> }
>
> -/* PASID */
> -void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width,
> - bool exec_perm, bool priv_mod)
> +void pcie_pasid_common_init(PCIDevice *dev, uint16_t offset,
> + uint8_t pasid_width, bool exec_perm, bool priv_mod)
> {
> static const uint16_t control_reg_rw_mask = 0x07;
> uint16_t capability_reg;
>
> assert(pasid_width <= PCI_EXT_CAP_PASID_MAX_WIDTH);
> -
> - pcie_add_capability(dev, PCI_EXT_CAP_ID_PASID, PCI_PASID_VER, offset,
> - PCI_EXT_CAP_PASID_SIZEOF);
> -
> capability_reg = ((uint16_t)pasid_width) << PCI_PASID_CAP_WIDTH_SHIFT;
> capability_reg |= exec_perm ? PCI_PASID_CAP_EXEC : 0;
> capability_reg |= priv_mod ? PCI_PASID_CAP_PRIV : 0;
> @@ -1307,6 +1302,16 @@ void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width,
> pci_set_word(dev->wmask + offset + PCI_PASID_CTRL, control_reg_rw_mask);
>
> dev->exp.pasid_cap = offset;
> +
> +}
> +
> +/* PASID */
> +void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width,
> + bool exec_perm, bool priv_mod)
> +{
> + pcie_add_capability(dev, PCI_EXT_CAP_ID_PASID, PCI_PASID_VER, offset,
> + PCI_EXT_CAP_PASID_SIZEOF);
> + pcie_pasid_common_init(dev, offset, pasid_width, exec_perm, priv_mod);
> }
>
> /* PRI */
> diff --git a/include/hw/pci/pcie.h b/include/hw/pci/pcie.h
> index d68bfa6257..fc02aeb169 100644
> --- a/include/hw/pci/pcie.h
> +++ b/include/hw/pci/pcie.h
> @@ -155,6 +155,8 @@ void pcie_cap_slot_unplug_cb(HotplugHandler *hotplug_dev, DeviceState *dev,
> void pcie_cap_slot_unplug_request_cb(HotplugHandler *hotplug_dev,
> DeviceState *dev, Error **errp);
>
> +void pcie_pasid_common_init(PCIDevice *dev, uint16_t offset,
> + uint8_t pasid_width, bool exec_perm, bool priv_mod);
> void pcie_pasid_init(PCIDevice *dev, uint16_t offset, uint8_t pasid_width,
> bool exec_perm, bool priv_mod);
> void pcie_pri_init(PCIDevice *dev, uint16_t offset, uint32_t outstanding_pr_cap,