riscv: correct fractional LMUL legality check in vsetvl

[PATCH] riscv: correct fractional LMUL legality check in vsetvl

Ridham Khurana posted 1 patch 1 week, 5 days ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20260125085958.47957-1-khurana.ridham222@gmail.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/vector_helper.c | 12 +++---------
1 file changed, 3 insertions(+), 9 deletions(-)

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[PATCH] riscv: correct fractional LMUL legality check in vsetvl

Posted by Ridham Khurana 1 week, 5 days ago

---
 target/riscv/vector_helper.c | 12 +++---------
 1 file changed, 3 insertions(+), 9 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 2de3358ee8..eff349841a 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -47,18 +47,12 @@ target_ulong HELPER(vsetvl)(CPURISCVState *env, target_ulong s1,
     target_ulong reserved = s2 &
                             MAKE_64BIT_MASK(R_VTYPE_RESERVED_SHIFT,
                                             xlen - 1 - R_VTYPE_RESERVED_SHIFT);
-    uint16_t vlen = cpu->cfg.vlenb << 3;
     int8_t lmul;
 
     if (vlmul & 4) {
-        /*
-         * Fractional LMUL, check:
-         *
-         * VLEN * LMUL >= SEW
-         * VLEN >> (8 - lmul) >= sew
-         * (vlenb << 3) >> (8 - lmul) >= sew
-         */
-        if (vlmul == 4 || (vlen >> (8 - vlmul)) < sew) {
+        /* fractional LMUL legality check: LMUL × ELEN ≥ SEW */
+        int divisor = 1 << (8 - vlmul); /* converts encoding into divisor for fractional LMUL */
+        if (vlmul == 4 || cpu->cfg.elen < sew * divisor) {
             vill = true;
         }
     }
-- 
2.49.0