Hi,

Changes since v7:
 https://lore.kernel.org/qemu-devel/20260111195508.106943-1-skolothumtho@nvidia.com/
 -Addressed comments and collected R-by and T-by tags. Thanks!.
 -Rebased to latest master.
 -Reworked PASID support patches (patch #34, #36).

I think this series is in good shape now and mature enough for inclusion.

Patch organization:

1–28: Enable accelerated SMMUv3 with features aligned to the default QEMU
SMMUv3 implementation, including IORT RMR-based MSI support.

29–31: Add user-configurable options for RIL, ATS, and OAS features.

32–37: Add PASID support, including required VFIO changes.

Please take a look and let me know your feedback.

Thanks,
Shameer

A complete branch can be found here,
https://github.com/shamiali2008/qemu-master/tree/master-smmuv3-accel-v8-dmabuf-v4

Testing:
 Basic sanity testing was performed on an NVIDIA Grace platform with GPU
 device assignment. A CUDA test application was used to validate the SVA
 use case. Additional testing and feedback are welcome.

Eg: Qemu Cmd line:

qemu-system-aarch64 -machine virt,gic-version=3,highmem-mmio-size=2T \
-cpu host -smp cpus=4 -m size=16G,slots=2,maxmem=66G -nographic \
-bios QEMU_EFI.fd -object iommufd,id=iommufd0 -enable-kvm \
-object memory-backend-ram,size=8G,id=m0 \
-object memory-backend-ram,size=8G,id=m1 \
-numa node,memdev=m0,cpus=0-3,nodeid=0 -numa node,memdev=m1,nodeid=1 \
-numa node,nodeid=2 -numa node,nodeid=3 -numa node,nodeid=4 -numa node,nodeid=5 \
-numa node,nodeid=6 -numa node,nodeid=7 -numa node,nodeid=8 -numa node,nodeid=9 \
-device pxb-pcie,id=pcie.1,bus_nr=1,bus=pcie.0 \
-device arm-smmuv3,primary-bus=pcie.1,id=smmuv3.0,accel=on,ats=on,ril=off,ssidsize=20,oas=48 \
-device pcie-root-port,id=pcie.port1,bus=pcie.1,chassis=1,pref64-reserve=512G,id=dev0 \
-device vfio-pci,host=0019:06:00.0,rombar=0,id=dev0,iommufd=iommufd0,bus=pcie.port1,x-vpasid-cap-offset=0xff8 \
-object acpi-generic-initiator,id=gi0,pci-dev=dev0,node=2 \
...
-object acpi-generic-initiator,id=gi7,pci-dev=dev0,node=9 \
-device pxb-pcie,id=pcie.2,bus_nr=8,bus=pcie.0 \
-device arm-smmuv3,primary-bus=pcie.2,id=smmuv3.1,accel=on,ats=on,ril=off,ssidsize=20,oas=48 \
-device pcie-root-port,id=pcie.port2,bus=pcie.2,chassis=2,pref64-reserve=512G \
-device vfio-pci,host=0018:06:00.0,rombar=0,id=dev1,iommufd=iommufd0,bus=pcie.port2,x-vpasid-cap-offset=0xff8 \
-device virtio-blk-device,drive=fs \
-drive file=image.qcow2,index=0,media=disk,format=qcow2,if=none,id=fs \
-net none \
-nographic

Details from RFCv3 Cover letter:
-------------------------------
https://lore.kernel.org/qemu-devel/20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com/

This patch series introduces initial support for a user-creatable,
accelerated SMMUv3 device (-device arm-smmuv3,accel=on) in QEMU.

This is based on the user-creatable SMMUv3 device series [0].

Why this is needed:

On ARM, to enable vfio-pci pass-through devices in a VM, the host SMMUv3
must be set up in nested translation mode (Stage 1 + Stage 2), with
Stage 1 (S1) controlled by the guest and Stage 2 (S2) managed by the host.

This series introduces an optional accel property for the SMMUv3 device,
indicating that the guest will try to leverage host SMMUv3 features for
acceleration. By default, enabling accel configures the host SMMUv3 in
nested mode to support vfio-pci pass-through.

This new accelerated, user-creatable SMMUv3 device lets you:

 -Set up a VM with multiple SMMUv3s, each tied to a different physical SMMUv3
  on the host. Typically, you’d have multiple PCIe PXB root complexes in the
  VM (one per virtual NUMA node), and each of them can have its own SMMUv3.
  This setup mirrors the host's layout, where each NUMA node has its own
  SMMUv3, and helps build VMs that are more aligned with the host's NUMA
  topology.

 -The host–guest SMMUv3 association results in reduced invalidation broadcasts
  and lookups for devices behind different physical SMMUv3s.

 -Simplifies handling of host SMMUv3s with differing feature sets.

 -Lays the groundwork for additional capabilities like vCMDQ support.
-------------------------------

Eric Auger (2):
  hw/pci-host/gpex: Allow to generate preserve boot config DSM #5
  hw/arm/virt-acpi-build: Add IORT RMR regions to handle MSI nested
    binding

Nicolin Chen (4):
  backends/iommufd: Introduce iommufd_backend_alloc_viommu
  backends/iommufd: Introduce iommufd_backend_alloc_vdev
  hw/arm/smmuv3-accel: Add set/unset_iommu_device callback
  hw/arm/smmuv3-accel: Add nested vSTE install/uninstall support

Shameer Kolothum (31):
  hw/arm/smmu-common: Factor out common helper functions and export
  hw/arm/smmu-common: Make iommu ops part of SMMUState
  hw/arm/smmuv3-accel: Introduce smmuv3 accel device
  hw/arm/smmuv3-accel: Initialize shared system address space
  hw/pci/pci: Move pci_init_bus_master() after adding device to bus
  hw/pci/pci: Add optional supports_address_space() callback
  hw/pci-bridge/pci_expander_bridge: Move TYPE_PXB_PCIE_DEV to header
  hw/arm/smmuv3-accel: Restrict accelerated SMMUv3 to vfio-pci endpoints
    with iommufd
  hw/arm/smmuv3: Implement get_viommu_cap() callback
  hw/arm/smmuv3: propagate smmuv3_cmdq_consume() errors to caller
  hw/arm/smmuv3-accel: Install SMMUv3 GBPA based hwpt
  hw/pci/pci: Introduce a callback to retrieve the MSI doorbell GPA
    directly
  hw/arm/smmuv3-accel: Implement get_msi_direct_gpa callback
  hw/arm/virt: Set msi-gpa property
  hw/arm/smmuv3-accel: Add support to issue invalidation cmd to host
  hw/arm/smmuv3: Initialize ID registers early during realize()
  hw/arm/smmuv3-accel: Get host SMMUv3 hw info and validate
  hw/arm/virt: Set PCI preserve_config for accel SMMUv3
  tests/qtest/bios-tables-test: Prepare for IORT revison upgrade
  tests/qtest/bios-tables-test: Update IORT blobs after revision upgrade
  hw/arm/smmuv3: Block migration when accel is enabled
  hw/arm/smmuv3: Add accel property for SMMUv3 device
  hw/arm/smmuv3-accel: Add a property to specify RIL support
  hw/arm/smmuv3-accel: Add support for ATS
  hw/arm/smmuv3-accel: Add property to specify OAS bits
  backends/iommufd: Retrieve PASID width from
    iommufd_backend_get_device_info()
  backends/iommufd: Add get_pasid_info() callback
  hw/pci: Add helper to insert PCIe extended capability at a fixed
    offset
  hw/pci: Factor out common PASID capability initialization
  hw/vfio/pci: Synthesize PASID capability for vfio-pci devices
  hw/arm/smmuv3-accel: Make SubstreamID support configurable

 backends/iommufd.c                            |  76 +-
 backends/trace-events                         |   2 +
 hw/arm/Kconfig                                |   5 +
 hw/arm/meson.build                            |   3 +-
 hw/arm/smmu-common.c                          |  51 +-
 hw/arm/smmuv3-accel.c                         | 768 ++++++++++++++++++
 hw/arm/smmuv3-accel.h                         |  88 ++
 hw/arm/smmuv3-internal.h                      |   1 +
 hw/arm/smmuv3.c                               | 227 +++++-
 hw/arm/trace-events                           |   6 +
 hw/arm/virt-acpi-build.c                      | 127 ++-
 hw/arm/virt.c                                 |  39 +-
 hw/pci-bridge/pci_expander_bridge.c           |   1 -
 hw/pci-host/gpex-acpi.c                       |  29 +-
 hw/pci/pci.c                                  |  43 +-
 hw/pci/pcie.c                                 |  88 +-
 hw/vfio/iommufd.c                             |   6 +-
 hw/vfio/pci.c                                 |  75 ++
 hw/vfio/pci.h                                 |   1 +
 hw/vfio/trace-events                          |   1 +
 include/hw/arm/smmu-common.h                  |   7 +
 include/hw/arm/smmuv3-common.h                |  27 +-
 include/hw/arm/smmuv3.h                       |  10 +
 include/hw/arm/virt.h                         |   1 +
 include/hw/core/iommu.h                       |   1 +
 include/hw/pci-host/gpex.h                    |   1 +
 include/hw/pci/pci.h                          |  36 +
 include/hw/pci/pci_bridge.h                   |   1 +
 include/hw/pci/pcie.h                         |   4 +
 include/system/host_iommu_device.h            |  20 +
 include/system/iommufd.h                      |  29 +-
 target/arm/kvm.c                              |  18 +-
 tests/data/acpi/aarch64/virt/IORT             | Bin 128 -> 128 bytes
 tests/data/acpi/aarch64/virt/IORT.its_off     | Bin 172 -> 172 bytes
 tests/data/acpi/aarch64/virt/IORT.smmuv3-dev  | Bin 364 -> 364 bytes
 .../data/acpi/aarch64/virt/IORT.smmuv3-legacy | Bin 276 -> 276 bytes
 36 files changed, 1692 insertions(+), 100 deletions(-)
 create mode 100644 hw/arm/smmuv3-accel.c
 create mode 100644 hw/arm/smmuv3-accel.h

-- 
2.43.0

On Thu, 22 Jan 2026 at 01:55, Shameer Kolothum <skolothumtho@nvidia.com> wrote:
>
> Hi,
>
> Changes since v7:
>  https://lore.kernel.org/qemu-devel/20260111195508.106943-1-skolothumtho@nvidia.com/
>  -Addressed comments and collected R-by and T-by tags. Thanks!.
>  -Rebased to latest master.
>  -Reworked PASID support patches (patch #34, #36).
>
> I think this series is in good shape now and mature enough for inclusion.
>
> Patch organization:
>
> 1–28: Enable accelerated SMMUv3 with features aligned to the default QEMU
> SMMUv3 implementation, including IORT RMR-based MSI support.
>
> 29–31: Add user-configurable options for RIL, ATS, and OAS features.
>
> 32–37: Add PASID support, including required VFIO changes.
>
> Please take a look and let me know your feedback.
>
> Thanks,
> Shameer
>
> A complete branch can be found here,
> https://github.com/shamiali2008/qemu-master/tree/master-smmuv3-accel-v8-dmabuf-v4


Thanks Shameer

Retested ok
https://github.com/Linaro/qemu/tree/master-smmuv3-accel-v8

Hi Peter, Richard,

On 1/21/26 6:52 PM, Shameer Kolothum wrote:
> Hi,
>
> Changes since v7:
>  https://lore.kernel.org/qemu-devel/20260111195508.106943-1-skolothumtho@nvidia.com/
>  -Addressed comments and collected R-by and T-by tags. Thanks!.
>  -Rebased to latest master.
>  -Reworked PASID support patches (patch #34, #36).
>
> I think this series is in good shape now and mature enough for inclusion.
>
> Patch organization:
>
> 1–28: Enable accelerated SMMUv3 with features aligned to the default QEMU
> SMMUv3 implementation, including IORT RMR-based MSI support.
>
> 29–31: Add user-configurable options for RIL, ATS, and OAS features.
>
> 32–37: Add PASID support, including required VFIO changes.
>
> Please take a look and let me know your feedback.

This big series collected R-b's and T-bs for all patches I think. Please
could you consider pulling it?

Thank you in advance

Eric
>
> Thanks,
> Shameer
>
> A complete branch can be found here,
> https://github.com/shamiali2008/qemu-master/tree/master-smmuv3-accel-v8-dmabuf-v4
>
> Testing:
>  Basic sanity testing was performed on an NVIDIA Grace platform with GPU
>  device assignment. A CUDA test application was used to validate the SVA
>  use case. Additional testing and feedback are welcome.
>
> Eg: Qemu Cmd line:
>
> qemu-system-aarch64 -machine virt,gic-version=3,highmem-mmio-size=2T \
> -cpu host -smp cpus=4 -m size=16G,slots=2,maxmem=66G -nographic \
> -bios QEMU_EFI.fd -object iommufd,id=iommufd0 -enable-kvm \
> -object memory-backend-ram,size=8G,id=m0 \
> -object memory-backend-ram,size=8G,id=m1 \
> -numa node,memdev=m0,cpus=0-3,nodeid=0 -numa node,memdev=m1,nodeid=1 \
> -numa node,nodeid=2 -numa node,nodeid=3 -numa node,nodeid=4 -numa node,nodeid=5 \
> -numa node,nodeid=6 -numa node,nodeid=7 -numa node,nodeid=8 -numa node,nodeid=9 \
> -device pxb-pcie,id=pcie.1,bus_nr=1,bus=pcie.0 \
> -device arm-smmuv3,primary-bus=pcie.1,id=smmuv3.0,accel=on,ats=on,ril=off,ssidsize=20,oas=48 \
> -device pcie-root-port,id=pcie.port1,bus=pcie.1,chassis=1,pref64-reserve=512G,id=dev0 \
> -device vfio-pci,host=0019:06:00.0,rombar=0,id=dev0,iommufd=iommufd0,bus=pcie.port1,x-vpasid-cap-offset=0xff8 \
> -object acpi-generic-initiator,id=gi0,pci-dev=dev0,node=2 \
> ...
> -object acpi-generic-initiator,id=gi7,pci-dev=dev0,node=9 \
> -device pxb-pcie,id=pcie.2,bus_nr=8,bus=pcie.0 \
> -device arm-smmuv3,primary-bus=pcie.2,id=smmuv3.1,accel=on,ats=on,ril=off,ssidsize=20,oas=48 \
> -device pcie-root-port,id=pcie.port2,bus=pcie.2,chassis=2,pref64-reserve=512G \
> -device vfio-pci,host=0018:06:00.0,rombar=0,id=dev1,iommufd=iommufd0,bus=pcie.port2,x-vpasid-cap-offset=0xff8 \
> -device virtio-blk-device,drive=fs \
> -drive file=image.qcow2,index=0,media=disk,format=qcow2,if=none,id=fs \
> -net none \
> -nographic
>
> Details from RFCv3 Cover letter:
> -------------------------------
> https://lore.kernel.org/qemu-devel/20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com/
>
> This patch series introduces initial support for a user-creatable,
> accelerated SMMUv3 device (-device arm-smmuv3,accel=on) in QEMU.
>
> This is based on the user-creatable SMMUv3 device series [0].
>
> Why this is needed:
>
> On ARM, to enable vfio-pci pass-through devices in a VM, the host SMMUv3
> must be set up in nested translation mode (Stage 1 + Stage 2), with
> Stage 1 (S1) controlled by the guest and Stage 2 (S2) managed by the host.
>
> This series introduces an optional accel property for the SMMUv3 device,
> indicating that the guest will try to leverage host SMMUv3 features for
> acceleration. By default, enabling accel configures the host SMMUv3 in
> nested mode to support vfio-pci pass-through.
>
> This new accelerated, user-creatable SMMUv3 device lets you:
>
>  -Set up a VM with multiple SMMUv3s, each tied to a different physical SMMUv3
>   on the host. Typically, you’d have multiple PCIe PXB root complexes in the
>   VM (one per virtual NUMA node), and each of them can have its own SMMUv3.
>   This setup mirrors the host's layout, where each NUMA node has its own
>   SMMUv3, and helps build VMs that are more aligned with the host's NUMA
>   topology.
>
>  -The host–guest SMMUv3 association results in reduced invalidation broadcasts
>   and lookups for devices behind different physical SMMUv3s.
>
>  -Simplifies handling of host SMMUv3s with differing feature sets.
>
>  -Lays the groundwork for additional capabilities like vCMDQ support.
> -------------------------------
>
> Eric Auger (2):
>   hw/pci-host/gpex: Allow to generate preserve boot config DSM #5
>   hw/arm/virt-acpi-build: Add IORT RMR regions to handle MSI nested
>     binding
>
> Nicolin Chen (4):
>   backends/iommufd: Introduce iommufd_backend_alloc_viommu
>   backends/iommufd: Introduce iommufd_backend_alloc_vdev
>   hw/arm/smmuv3-accel: Add set/unset_iommu_device callback
>   hw/arm/smmuv3-accel: Add nested vSTE install/uninstall support
>
> Shameer Kolothum (31):
>   hw/arm/smmu-common: Factor out common helper functions and export
>   hw/arm/smmu-common: Make iommu ops part of SMMUState
>   hw/arm/smmuv3-accel: Introduce smmuv3 accel device
>   hw/arm/smmuv3-accel: Initialize shared system address space
>   hw/pci/pci: Move pci_init_bus_master() after adding device to bus
>   hw/pci/pci: Add optional supports_address_space() callback
>   hw/pci-bridge/pci_expander_bridge: Move TYPE_PXB_PCIE_DEV to header
>   hw/arm/smmuv3-accel: Restrict accelerated SMMUv3 to vfio-pci endpoints
>     with iommufd
>   hw/arm/smmuv3: Implement get_viommu_cap() callback
>   hw/arm/smmuv3: propagate smmuv3_cmdq_consume() errors to caller
>   hw/arm/smmuv3-accel: Install SMMUv3 GBPA based hwpt
>   hw/pci/pci: Introduce a callback to retrieve the MSI doorbell GPA
>     directly
>   hw/arm/smmuv3-accel: Implement get_msi_direct_gpa callback
>   hw/arm/virt: Set msi-gpa property
>   hw/arm/smmuv3-accel: Add support to issue invalidation cmd to host
>   hw/arm/smmuv3: Initialize ID registers early during realize()
>   hw/arm/smmuv3-accel: Get host SMMUv3 hw info and validate
>   hw/arm/virt: Set PCI preserve_config for accel SMMUv3
>   tests/qtest/bios-tables-test: Prepare for IORT revison upgrade
>   tests/qtest/bios-tables-test: Update IORT blobs after revision upgrade
>   hw/arm/smmuv3: Block migration when accel is enabled
>   hw/arm/smmuv3: Add accel property for SMMUv3 device
>   hw/arm/smmuv3-accel: Add a property to specify RIL support
>   hw/arm/smmuv3-accel: Add support for ATS
>   hw/arm/smmuv3-accel: Add property to specify OAS bits
>   backends/iommufd: Retrieve PASID width from
>     iommufd_backend_get_device_info()
>   backends/iommufd: Add get_pasid_info() callback
>   hw/pci: Add helper to insert PCIe extended capability at a fixed
>     offset
>   hw/pci: Factor out common PASID capability initialization
>   hw/vfio/pci: Synthesize PASID capability for vfio-pci devices
>   hw/arm/smmuv3-accel: Make SubstreamID support configurable
>
>  backends/iommufd.c                            |  76 +-
>  backends/trace-events                         |   2 +
>  hw/arm/Kconfig                                |   5 +
>  hw/arm/meson.build                            |   3 +-
>  hw/arm/smmu-common.c                          |  51 +-
>  hw/arm/smmuv3-accel.c                         | 768 ++++++++++++++++++
>  hw/arm/smmuv3-accel.h                         |  88 ++
>  hw/arm/smmuv3-internal.h                      |   1 +
>  hw/arm/smmuv3.c                               | 227 +++++-
>  hw/arm/trace-events                           |   6 +
>  hw/arm/virt-acpi-build.c                      | 127 ++-
>  hw/arm/virt.c                                 |  39 +-
>  hw/pci-bridge/pci_expander_bridge.c           |   1 -
>  hw/pci-host/gpex-acpi.c                       |  29 +-
>  hw/pci/pci.c                                  |  43 +-
>  hw/pci/pcie.c                                 |  88 +-
>  hw/vfio/iommufd.c                             |   6 +-
>  hw/vfio/pci.c                                 |  75 ++
>  hw/vfio/pci.h                                 |   1 +
>  hw/vfio/trace-events                          |   1 +
>  include/hw/arm/smmu-common.h                  |   7 +
>  include/hw/arm/smmuv3-common.h                |  27 +-
>  include/hw/arm/smmuv3.h                       |  10 +
>  include/hw/arm/virt.h                         |   1 +
>  include/hw/core/iommu.h                       |   1 +
>  include/hw/pci-host/gpex.h                    |   1 +
>  include/hw/pci/pci.h                          |  36 +
>  include/hw/pci/pci_bridge.h                   |   1 +
>  include/hw/pci/pcie.h                         |   4 +
>  include/system/host_iommu_device.h            |  20 +
>  include/system/iommufd.h                      |  29 +-
>  target/arm/kvm.c                              |  18 +-
>  tests/data/acpi/aarch64/virt/IORT             | Bin 128 -> 128 bytes
>  tests/data/acpi/aarch64/virt/IORT.its_off     | Bin 172 -> 172 bytes
>  tests/data/acpi/aarch64/virt/IORT.smmuv3-dev  | Bin 364 -> 364 bytes
>  .../data/acpi/aarch64/virt/IORT.smmuv3-legacy | Bin 276 -> 276 bytes
>  36 files changed, 1692 insertions(+), 100 deletions(-)
>  create mode 100644 hw/arm/smmuv3-accel.c
>  create mode 100644 hw/arm/smmuv3-accel.h
>

On Fri, 23 Jan 2026 08:55:18 +0100
Eric Auger <eric.auger@redhat.com> wrote:

> Hi Peter, Richard,
> 
> On 1/21/26 6:52 PM, Shameer Kolothum wrote:
> > Hi,
> >
> > Changes since v7:
> >  https://lore.kernel.org/qemu-devel/20260111195508.106943-1-skolothumtho@nvidia.com/
> >  -Addressed comments and collected R-by and T-by tags. Thanks!.
> >  -Rebased to latest master.
> >  -Reworked PASID support patches (patch #34, #36).
> >
> > I think this series is in good shape now and mature enough for inclusion.
> >
> > Patch organization:
> >
> > 1–28: Enable accelerated SMMUv3 with features aligned to the default QEMU
> > SMMUv3 implementation, including IORT RMR-based MSI support.
> >
> > 29–31: Add user-configurable options for RIL, ATS, and OAS features.
> >
> > 32–37: Add PASID support, including required VFIO changes.
> >
> > Please take a look and let me know your feedback.  
> 
> This big series collected R-b's and T-bs for all patches I think. Please
> could you consider pulling it?

I definitely support getting this merged now.

I'm seeing an indent snafu in patch 18 though which either Shameer needs
to tidy up in a v9 or it needs a bit of hand tweaking by the person
queuing this up for a pull request.

Jonathan

> 
> Thank you in advance
> 
> Eric
> >
> > Thanks,
> > Shameer
> >
> > A complete branch can be found here,
> > https://github.com/shamiali2008/qemu-master/tree/master-smmuv3-accel-v8-dmabuf-v4
> >
> > Testing:
> >  Basic sanity testing was performed on an NVIDIA Grace platform with GPU
> >  device assignment. A CUDA test application was used to validate the SVA
> >  use case. Additional testing and feedback are welcome.
> >
> > Eg: Qemu Cmd line:
> >
> > qemu-system-aarch64 -machine virt,gic-version=3,highmem-mmio-size=2T \
> > -cpu host -smp cpus=4 -m size=16G,slots=2,maxmem=66G -nographic \
> > -bios QEMU_EFI.fd -object iommufd,id=iommufd0 -enable-kvm \
> > -object memory-backend-ram,size=8G,id=m0 \
> > -object memory-backend-ram,size=8G,id=m1 \
> > -numa node,memdev=m0,cpus=0-3,nodeid=0 -numa node,memdev=m1,nodeid=1 \
> > -numa node,nodeid=2 -numa node,nodeid=3 -numa node,nodeid=4 -numa node,nodeid=5 \
> > -numa node,nodeid=6 -numa node,nodeid=7 -numa node,nodeid=8 -numa node,nodeid=9 \
> > -device pxb-pcie,id=pcie.1,bus_nr=1,bus=pcie.0 \
> > -device arm-smmuv3,primary-bus=pcie.1,id=smmuv3.0,accel=on,ats=on,ril=off,ssidsize=20,oas=48 \
> > -device pcie-root-port,id=pcie.port1,bus=pcie.1,chassis=1,pref64-reserve=512G,id=dev0 \
> > -device vfio-pci,host=0019:06:00.0,rombar=0,id=dev0,iommufd=iommufd0,bus=pcie.port1,x-vpasid-cap-offset=0xff8 \
> > -object acpi-generic-initiator,id=gi0,pci-dev=dev0,node=2 \
> > ...
> > -object acpi-generic-initiator,id=gi7,pci-dev=dev0,node=9 \
> > -device pxb-pcie,id=pcie.2,bus_nr=8,bus=pcie.0 \
> > -device arm-smmuv3,primary-bus=pcie.2,id=smmuv3.1,accel=on,ats=on,ril=off,ssidsize=20,oas=48 \
> > -device pcie-root-port,id=pcie.port2,bus=pcie.2,chassis=2,pref64-reserve=512G \
> > -device vfio-pci,host=0018:06:00.0,rombar=0,id=dev1,iommufd=iommufd0,bus=pcie.port2,x-vpasid-cap-offset=0xff8 \
> > -device virtio-blk-device,drive=fs \
> > -drive file=image.qcow2,index=0,media=disk,format=qcow2,if=none,id=fs \
> > -net none \
> > -nographic
> >
> > Details from RFCv3 Cover letter:
> > -------------------------------
> > https://lore.kernel.org/qemu-devel/20250714155941.22176-1-shameerali.kolothum.thodi@huawei.com/
> >
> > This patch series introduces initial support for a user-creatable,
> > accelerated SMMUv3 device (-device arm-smmuv3,accel=on) in QEMU.
> >
> > This is based on the user-creatable SMMUv3 device series [0].
> >
> > Why this is needed:
> >
> > On ARM, to enable vfio-pci pass-through devices in a VM, the host SMMUv3
> > must be set up in nested translation mode (Stage 1 + Stage 2), with
> > Stage 1 (S1) controlled by the guest and Stage 2 (S2) managed by the host.
> >
> > This series introduces an optional accel property for the SMMUv3 device,
> > indicating that the guest will try to leverage host SMMUv3 features for
> > acceleration. By default, enabling accel configures the host SMMUv3 in
> > nested mode to support vfio-pci pass-through.
> >
> > This new accelerated, user-creatable SMMUv3 device lets you:
> >
> >  -Set up a VM with multiple SMMUv3s, each tied to a different physical SMMUv3
> >   on the host. Typically, you’d have multiple PCIe PXB root complexes in the
> >   VM (one per virtual NUMA node), and each of them can have its own SMMUv3.
> >   This setup mirrors the host's layout, where each NUMA node has its own
> >   SMMUv3, and helps build VMs that are more aligned with the host's NUMA
> >   topology.
> >
> >  -The host–guest SMMUv3 association results in reduced invalidation broadcasts
> >   and lookups for devices behind different physical SMMUv3s.
> >
> >  -Simplifies handling of host SMMUv3s with differing feature sets.
> >
> >  -Lays the groundwork for additional capabilities like vCMDQ support.
> > -------------------------------
> >
> > Eric Auger (2):
> >   hw/pci-host/gpex: Allow to generate preserve boot config DSM #5
> >   hw/arm/virt-acpi-build: Add IORT RMR regions to handle MSI nested
> >     binding
> >
> > Nicolin Chen (4):
> >   backends/iommufd: Introduce iommufd_backend_alloc_viommu
> >   backends/iommufd: Introduce iommufd_backend_alloc_vdev
> >   hw/arm/smmuv3-accel: Add set/unset_iommu_device callback
> >   hw/arm/smmuv3-accel: Add nested vSTE install/uninstall support
> >
> > Shameer Kolothum (31):
> >   hw/arm/smmu-common: Factor out common helper functions and export
> >   hw/arm/smmu-common: Make iommu ops part of SMMUState
> >   hw/arm/smmuv3-accel: Introduce smmuv3 accel device
> >   hw/arm/smmuv3-accel: Initialize shared system address space
> >   hw/pci/pci: Move pci_init_bus_master() after adding device to bus
> >   hw/pci/pci: Add optional supports_address_space() callback
> >   hw/pci-bridge/pci_expander_bridge: Move TYPE_PXB_PCIE_DEV to header
> >   hw/arm/smmuv3-accel: Restrict accelerated SMMUv3 to vfio-pci endpoints
> >     with iommufd
> >   hw/arm/smmuv3: Implement get_viommu_cap() callback
> >   hw/arm/smmuv3: propagate smmuv3_cmdq_consume() errors to caller
> >   hw/arm/smmuv3-accel: Install SMMUv3 GBPA based hwpt
> >   hw/pci/pci: Introduce a callback to retrieve the MSI doorbell GPA
> >     directly
> >   hw/arm/smmuv3-accel: Implement get_msi_direct_gpa callback
> >   hw/arm/virt: Set msi-gpa property
> >   hw/arm/smmuv3-accel: Add support to issue invalidation cmd to host
> >   hw/arm/smmuv3: Initialize ID registers early during realize()
> >   hw/arm/smmuv3-accel: Get host SMMUv3 hw info and validate
> >   hw/arm/virt: Set PCI preserve_config for accel SMMUv3
> >   tests/qtest/bios-tables-test: Prepare for IORT revison upgrade
> >   tests/qtest/bios-tables-test: Update IORT blobs after revision upgrade
> >   hw/arm/smmuv3: Block migration when accel is enabled
> >   hw/arm/smmuv3: Add accel property for SMMUv3 device
> >   hw/arm/smmuv3-accel: Add a property to specify RIL support
> >   hw/arm/smmuv3-accel: Add support for ATS
> >   hw/arm/smmuv3-accel: Add property to specify OAS bits
> >   backends/iommufd: Retrieve PASID width from
> >     iommufd_backend_get_device_info()
> >   backends/iommufd: Add get_pasid_info() callback
> >   hw/pci: Add helper to insert PCIe extended capability at a fixed
> >     offset
> >   hw/pci: Factor out common PASID capability initialization
> >   hw/vfio/pci: Synthesize PASID capability for vfio-pci devices
> >   hw/arm/smmuv3-accel: Make SubstreamID support configurable
> >
> >  backends/iommufd.c                            |  76 +-
> >  backends/trace-events                         |   2 +
> >  hw/arm/Kconfig                                |   5 +
> >  hw/arm/meson.build                            |   3 +-
> >  hw/arm/smmu-common.c                          |  51 +-
> >  hw/arm/smmuv3-accel.c                         | 768 ++++++++++++++++++
> >  hw/arm/smmuv3-accel.h                         |  88 ++
> >  hw/arm/smmuv3-internal.h                      |   1 +
> >  hw/arm/smmuv3.c                               | 227 +++++-
> >  hw/arm/trace-events                           |   6 +
> >  hw/arm/virt-acpi-build.c                      | 127 ++-
> >  hw/arm/virt.c                                 |  39 +-
> >  hw/pci-bridge/pci_expander_bridge.c           |   1 -
> >  hw/pci-host/gpex-acpi.c                       |  29 +-
> >  hw/pci/pci.c                                  |  43 +-
> >  hw/pci/pcie.c                                 |  88 +-
> >  hw/vfio/iommufd.c                             |   6 +-
> >  hw/vfio/pci.c                                 |  75 ++
> >  hw/vfio/pci.h                                 |   1 +
> >  hw/vfio/trace-events                          |   1 +
> >  include/hw/arm/smmu-common.h                  |   7 +
> >  include/hw/arm/smmuv3-common.h                |  27 +-
> >  include/hw/arm/smmuv3.h                       |  10 +
> >  include/hw/arm/virt.h                         |   1 +
> >  include/hw/core/iommu.h                       |   1 +
> >  include/hw/pci-host/gpex.h                    |   1 +
> >  include/hw/pci/pci.h                          |  36 +
> >  include/hw/pci/pci_bridge.h                   |   1 +
> >  include/hw/pci/pcie.h                         |   4 +
> >  include/system/host_iommu_device.h            |  20 +
> >  include/system/iommufd.h                      |  29 +-
> >  target/arm/kvm.c                              |  18 +-
> >  tests/data/acpi/aarch64/virt/IORT             | Bin 128 -> 128 bytes
> >  tests/data/acpi/aarch64/virt/IORT.its_off     | Bin 172 -> 172 bytes
> >  tests/data/acpi/aarch64/virt/IORT.smmuv3-dev  | Bin 364 -> 364 bytes
> >  .../data/acpi/aarch64/virt/IORT.smmuv3-legacy | Bin 276 -> 276 bytes
> >  36 files changed, 1692 insertions(+), 100 deletions(-)
> >  create mode 100644 hw/arm/smmuv3-accel.c
> >  create mode 100644 hw/arm/smmuv3-accel.h
> >  
> 
> 

On Fri, 23 Jan 2026 at 11:41, Jonathan Cameron
<jonathan.cameron@huawei.com> wrote:
>
> On Fri, 23 Jan 2026 08:55:18 +0100
> Eric Auger <eric.auger@redhat.com> wrote:
>
> > Hi Peter, Richard,
> >
> > On 1/21/26 6:52 PM, Shameer Kolothum wrote:
> > > Hi,
> > >
> > > Changes since v7:
> > >  https://lore.kernel.org/qemu-devel/20260111195508.106943-1-skolothumtho@nvidia.com/
> > >  -Addressed comments and collected R-by and T-by tags. Thanks!.
> > >  -Rebased to latest master.
> > >  -Reworked PASID support patches (patch #34, #36).
> > >
> > > I think this series is in good shape now and mature enough for inclusion.
> > >
> > > Patch organization:
> > >
> > > 1–28: Enable accelerated SMMUv3 with features aligned to the default QEMU
> > > SMMUv3 implementation, including IORT RMR-based MSI support.
> > >
> > > 29–31: Add user-configurable options for RIL, ATS, and OAS features.
> > >
> > > 32–37: Add PASID support, including required VFIO changes.
> > >
> > > Please take a look and let me know your feedback.
> >
> > This big series collected R-b's and T-bs for all patches I think. Please
> > could you consider pulling it?
>
> I definitely support getting this merged now.
>
> I'm seeing an indent snafu in patch 18 though which either Shameer needs
> to tidy up in a v9 or it needs a bit of hand tweaking by the person
> queuing this up for a pull request.

I can fix that up when I queue it into target-arm.next.

Thanks to everybody who helped with code review on this series:
not having to do that myself has been a big help for my personal
workload :-)

-- PMM

> -----Original Message-----
> From: Peter Maydell <peter.maydell@linaro.org>
> Sent: 23 January 2026 11:59
> To: Jonathan Cameron <jonathan.cameron@huawei.com>
> Cc: Eric Auger <eric.auger@redhat.com>; Shameer Kolothum
> <skolothumtho@nvidia.com>; qemu-arm@nongnu.org; qemu-
> devel@nongnu.org; Richard Henderson <richard.henderson@linaro.org>;
> Jason Gunthorpe <jgg@nvidia.com>; Nicolin Chen <nicolinc@nvidia.com>;
> ddutile@redhat.com; berrange@redhat.com; clg@redhat.com;
> alex@shazbot.org; Nathan Chen <nathanc@nvidia.com>; Matt Ochs
> <mochs@nvidia.com>; smostafa@google.com; wangzhou1@hisilicon.com;
> jiangkunkun@huawei.com; zhangfei.gao@linaro.org;
> zhenzhong.duan@intel.com; yi.l.liu@intel.com; Krishnakant Jaju
> <kjaju@nvidia.com>
> Subject: Re: [PATCH v8 00/37] hw/arm/virt: Add support for user-creatable
> accelerated SMMUv3
> 
> External email: Use caution opening links or attachments
> 
> 
> On Fri, 23 Jan 2026 at 11:41, Jonathan Cameron
> <jonathan.cameron@huawei.com> wrote:
> >
> > On Fri, 23 Jan 2026 08:55:18 +0100
> > Eric Auger <eric.auger@redhat.com> wrote:
> >
> > > Hi Peter, Richard,
> > >
> > > On 1/21/26 6:52 PM, Shameer Kolothum wrote:
> > > > Hi,
> > > >
> > > > Changes since v7:
> > > >
> > > >
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2F
> > > > lore.kernel.org%2Fqemu-devel%2F20260111195508.106943-1-
> skolothumth
> > > >
> o%40nvidia.com%2F&data=05%7C02%7Cskolothumtho%40nvidia.com%7C4
> dc79
> > > >
> 79cc1814987fccc08de5a76c402%7C43083d15727340c1b7db39efd9ccc17a
> %7C0
> > > >
> %7C0%7C639047663322567693%7CUnknown%7CTWFpbGZsb3d8eyJFbXB
> 0eU1hcGki
> > > >
> OnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIj
> > > >
> oyfQ%3D%3D%7C0%7C%7C%7C&sdata=H26lLiSX8ItkQJgPVvhVPz5aJwwVIo
> sVwSEP
> > > > NjvKjS4%3D&reserved=0  -Addressed comments and collected R-by and
> > > > T-by tags. Thanks!.
> > > >  -Rebased to latest master.
> > > >  -Reworked PASID support patches (patch #34, #36).
> > > >
> > > > I think this series is in good shape now and mature enough for inclusion.
> > > >
> > > > Patch organization:
> > > >
> > > > 1-28: Enable accelerated SMMUv3 with features aligned to the
> > > > default QEMU
> > > > SMMUv3 implementation, including IORT RMR-based MSI support.
> > > >
> > > > 29-31: Add user-configurable options for RIL, ATS, and OAS features.
> > > >
> > > > 32-37: Add PASID support, including required VFIO changes.
> > > >
> > > > Please take a look and let me know your feedback.
> > >
> > > This big series collected R-b's and T-bs for all patches I think.
> > > Please could you consider pulling it?
> >
> > I definitely support getting this merged now.
> >
> > I'm seeing an indent snafu in patch 18 though which either Shameer
> > needs to tidy up in a v9 or it needs a bit of hand tweaking by the
> > person queuing this up for a pull request.
> 
> I can fix that up when I queue it into target-arm.next.
> 
> Thanks to everybody who helped with code review on this series:
> not having to do that myself has been a big help for my personal workload :-)

Thanks for sorting it while queuing.

And cheers everyone for the reviews and help!

Shameer

On Fri, 23 Jan 2026 at 12:04, Shameer Kolothum <skolothumtho@nvidia.com> wrote:
> > From: Peter Maydell <peter.maydell@linaro.org>
> > I can fix that up when I queue it into target-arm.next.
> >
> > Thanks to everybody who helped with code review on this series:
> > not having to do that myself has been a big help for my personal workload :-)
>
> Thanks for sorting it while queuing.

Unfortunately I had to drop this from target-arm.next,
because it caused one of the gitlab CI jobs to fail:
https://gitlab.com/pm215/qemu/-/jobs/12839040278
(Not an intermittent -- the job failed the same way
on retry, and passes with my target-arm queue without
this series in it.)

I'm not sure exactly what's going on here, because
the bios-tables-test test passes on my local machine.
Could you investigate, please?

1/457 qemu:qtest+qtest-x86_64 / qtest-x86_64/bios-tables-test OK
83.58s 55 subtests passed
▶ 2/457 /aarch64/acpi/virt/its_off -
ERROR:../tests/qtest/bios-tables-test.c:554:test_acpi_asl: assertion
failed: (all_tables_match) FAIL
▶ 2/457 ERROR
2/457 qemu:qtest+qtest-aarch64 / qtest-aarch64/bios-tables-test ERROR
25.86s killed by signal 6 SIGABRT
>>> MSAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1:print_stacktrace=1 PYTHON=/builds/pm215/qemu/build/pyvenv/bin/python3.11 UBSAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1:print_stacktrace=1 QTEST_QEMU_IMG=./qemu-img QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-storage-daemon ASAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1 RUST_BACKTRACE=1 MESON_TEST_ITERATION=1 G_TEST_DBUS_DAEMON=/builds/pm215/qemu/tests/dbus-vmstate-daemon.sh MALLOC_PERTURB_=162 QTEST_QEMU_BINARY=./qemu-system-aarch64 /builds/pm215/qemu/build/tests/qtest/bios-tables-test --tap -k
――――――――――――――――――――――――――――――――――――― ✀ ―――――――――――――――――――――――――――――――――――――
stderr:
acpi-test: Warning! IORT binary file mismatch. Actual
[aml:/tmp/aml-7QQVJ3], Expected
[aml:tests/data/acpi/aarch64/virt/IORT.its_off].
See source file tests/qtest/bios-tables-test.c for instructions on how
to update expected files.
to see ASL diff between mismatched files install IASL, rebuild QEMU
from scratch and re-run tests with V=1 environment variable set**
ERROR:../tests/qtest/bios-tables-test.c:554:test_acpi_asl: assertion
failed: (all_tables_match)
(test program exited with status code -6)


thanks
-- PMM

> -----Original Message-----
> From: Peter Maydell <peter.maydell@linaro.org>
> Sent: 23 January 2026 15:06
> To: Shameer Kolothum <skolothumtho@nvidia.com>
> Cc: Jonathan Cameron <jonathan.cameron@huawei.com>; Eric Auger
> <eric.auger@redhat.com>; qemu-arm@nongnu.org; qemu-
> devel@nongnu.org; Richard Henderson <richard.henderson@linaro.org>;
> Jason Gunthorpe <jgg@nvidia.com>; Nicolin Chen <nicolinc@nvidia.com>;
> ddutile@redhat.com; berrange@redhat.com; clg@redhat.com;
> alex@shazbot.org; Nathan Chen <nathanc@nvidia.com>; Matt Ochs
> <mochs@nvidia.com>; smostafa@google.com; wangzhou1@hisilicon.com;
> jiangkunkun@huawei.com; zhangfei.gao@linaro.org;
> zhenzhong.duan@intel.com; yi.l.liu@intel.com; Krishnakant Jaju
> <kjaju@nvidia.com>
> Subject: Re: [PATCH v8 00/37] hw/arm/virt: Add support for user-creatable
> accelerated SMMUv3
> 
> External email: Use caution opening links or attachments
> 
> 
> On Fri, 23 Jan 2026 at 12:04, Shameer Kolothum
> <skolothumtho@nvidia.com> wrote:
> > > From: Peter Maydell <peter.maydell@linaro.org>
> > > I can fix that up when I queue it into target-arm.next.
> > >
> > > Thanks to everybody who helped with code review on this series:
> > > not having to do that myself has been a big help for my personal workload
> :-)
> >
> > Thanks for sorting it while queuing.
> 
> Unfortunately I had to drop this from target-arm.next,
> because it caused one of the gitlab CI jobs to fail:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitla
> b.com%2Fpm215%2Fqemu%2F-
> %2Fjobs%2F12839040278&data=05%7C02%7Cskolothumtho%40nvidia.co
> m%7Ce64f88e5ebe54c10a77008de5a90f12d%7C43083d15727340c1b7db
> 39efd9ccc17a%7C0%7C0%7C639047775811752760%7CUnknown%7CTWF
> pbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW
> 4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=r2cFx
> te6tcUSLjTTpMKMvmU4g7FgrhMTatELkP4sJXo%3D&reserved=0
> (Not an intermittent -- the job failed the same way
> on retry, and passes with my target-arm queue without
> this series in it.)
> 
> I'm not sure exactly what's going on here, because
> the bios-tables-test test passes on my local machine.

I tried on both my ARM64 and x86 machine and no failure.

> Could you investigate, please?
> 
> 1/457 qemu:qtest+qtest-x86_64 / qtest-x86_64/bios-tables-test OK
> 83.58s 55 subtests passed
> ▶ 2/457 /aarch64/acpi/virt/its_off -

This is the one failing apparently.

> ERROR:../tests/qtest/bios-tables-test.c:554:test_acpi_asl: assertion
> failed: (all_tables_match) FAIL
> ▶ 2/457 ERROR
> 2/457 qemu:qtest+qtest-aarch64 / qtest-aarch64/bios-tables-test ERROR
> 25.86s killed by signal 6 SIGABRT
> >>>
> MSAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1:print
> _stacktrace=1 PYTHON=/builds/pm215/qemu/build/pyvenv/bin/python3.11
> UBSAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1:print
> _stacktrace=1 QTEST_QEMU_IMG=./qemu-img
> QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-
> storage-daemon
> ASAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1
> RUST_BACKTRACE=1 MESON_TEST_ITERATION=1
> G_TEST_DBUS_DAEMON=/builds/pm215/qemu/tests/dbus-vmstate-
> daemon.sh MALLOC_PERTURB_=162 QTEST_QEMU_BINARY=./qemu-system-
> aarch64 /builds/pm215/qemu/build/tests/qtest/bios-tables-test --tap -k
> ―――――――――――――――――――――――――――――――――
> ―――― ✀
> ―――――――――――――――――――――――――――――――――
> ――――
> stderr:
> acpi-test: Warning! IORT binary file mismatch. Actual
> [aml:/tmp/aml-7QQVJ3], Expected
> [aml:tests/data/acpi/aarch64/virt/IORT.its_off].

Any way to retrieve these files?

Thanks,
Shameer

On Fri, 23 Jan 2026 at 15:33, Shameer Kolothum <skolothumtho@nvidia.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Peter Maydell <peter.maydell@linaro.org>
> > Sent: 23 January 2026 15:06
> > To: Shameer Kolothum <skolothumtho@nvidia.com>
> > Cc: Jonathan Cameron <jonathan.cameron@huawei.com>; Eric Auger
> > <eric.auger@redhat.com>; qemu-arm@nongnu.org; qemu-
> > devel@nongnu.org; Richard Henderson <richard.henderson@linaro.org>;
> > Jason Gunthorpe <jgg@nvidia.com>; Nicolin Chen <nicolinc@nvidia.com>;
> > ddutile@redhat.com; berrange@redhat.com; clg@redhat.com;
> > alex@shazbot.org; Nathan Chen <nathanc@nvidia.com>; Matt Ochs
> > <mochs@nvidia.com>; smostafa@google.com; wangzhou1@hisilicon.com;
> > jiangkunkun@huawei.com; zhangfei.gao@linaro.org;
> > zhenzhong.duan@intel.com; yi.l.liu@intel.com; Krishnakant Jaju
> > <kjaju@nvidia.com>
> > Subject: Re: [PATCH v8 00/37] hw/arm/virt: Add support for user-creatable
> > accelerated SMMUv3
> >
> > External email: Use caution opening links or attachments
> >
> >
> > On Fri, 23 Jan 2026 at 12:04, Shameer Kolothum
> > <skolothumtho@nvidia.com> wrote:
> > > > From: Peter Maydell <peter.maydell@linaro.org>
> > > > I can fix that up when I queue it into target-arm.next.
> > > >
> > > > Thanks to everybody who helped with code review on this series:
> > > > not having to do that myself has been a big help for my personal workload
> > :-)
> > >
> > > Thanks for sorting it while queuing.
> >
> > Unfortunately I had to drop this from target-arm.next,
> > because it caused one of the gitlab CI jobs to fail:
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitla
> > b.com%2Fpm215%2Fqemu%2F-
> > %2Fjobs%2F12839040278&data=05%7C02%7Cskolothumtho%40nvidia.co
> > m%7Ce64f88e5ebe54c10a77008de5a90f12d%7C43083d15727340c1b7db
> > 39efd9ccc17a%7C0%7C0%7C639047775811752760%7CUnknown%7CTWF
> > pbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIwLjAuMDAwMCIsIlAiOiJXaW
> > 4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&sdata=r2cFx
> > te6tcUSLjTTpMKMvmU4g7FgrhMTatELkP4sJXo%3D&reserved=0
> > (Not an intermittent -- the job failed the same way
> > on retry, and passes with my target-arm queue without
> > this series in it.)
> >
> > I'm not sure exactly what's going on here, because
> > the bios-tables-test test passes on my local machine.
>
> I tried on both my ARM64 and x86 machine and no failure.
>
> > Could you investigate, please?
> >
> > 1/457 qemu:qtest+qtest-x86_64 / qtest-x86_64/bios-tables-test OK
> > 83.58s 55 subtests passed
> > ▶ 2/457 /aarch64/acpi/virt/its_off -
>
> This is the one failing apparently.
>
> > ERROR:../tests/qtest/bios-tables-test.c:554:test_acpi_asl: assertion
> > failed: (all_tables_match) FAIL
> > ▶ 2/457 ERROR
> > 2/457 qemu:qtest+qtest-aarch64 / qtest-aarch64/bios-tables-test ERROR
> > 25.86s killed by signal 6 SIGABRT
> > >>>
> > MSAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1:print
> > _stacktrace=1 PYTHON=/builds/pm215/qemu/build/pyvenv/bin/python3.11
> > UBSAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1:print
> > _stacktrace=1 QTEST_QEMU_IMG=./qemu-img
> > QTEST_QEMU_STORAGE_DAEMON_BINARY=./storage-daemon/qemu-
> > storage-daemon
> > ASAN_OPTIONS=halt_on_error=1:abort_on_error=1:print_summary=1
> > RUST_BACKTRACE=1 MESON_TEST_ITERATION=1
> > G_TEST_DBUS_DAEMON=/builds/pm215/qemu/tests/dbus-vmstate-
> > daemon.sh MALLOC_PERTURB_=162 QTEST_QEMU_BINARY=./qemu-system-
> > aarch64 /builds/pm215/qemu/build/tests/qtest/bios-tables-test --tap -k
> > ―――――――――――――――――――――――――――――――――
> > ―――― ✀
> > ―――――――――――――――――――――――――――――――――
> > ――――
> > stderr:
> > acpi-test: Warning! IORT binary file mismatch. Actual
> > [aml:/tmp/aml-7QQVJ3], Expected
> > [aml:tests/data/acpi/aarch64/virt/IORT.its_off].
>
> Any way to retrieve these files?

They aren't in the "job artifacts", but you can probably do
a patch to tweak the CI job to add them, push to your own
gitlab fork of QEMU to have it run the CI, and then look at
the results.

thanks
-- PMM

> -----Original Message-----
> From: Peter Maydell <peter.maydell@linaro.org>
> Sent: 23 January 2026 15:48
> To: Shameer Kolothum <skolothumtho@nvidia.com>
> Cc: Jonathan Cameron <jonathan.cameron@huawei.com>; Eric Auger
> <eric.auger@redhat.com>; qemu-arm@nongnu.org; qemu-
> devel@nongnu.org; Richard Henderson <richard.henderson@linaro.org>;
> Jason Gunthorpe <jgg@nvidia.com>; Nicolin Chen <nicolinc@nvidia.com>;
> ddutile@redhat.com; berrange@redhat.com; clg@redhat.com;
> alex@shazbot.org; Nathan Chen <nathanc@nvidia.com>; Matt Ochs
> <mochs@nvidia.com>; smostafa@google.com; wangzhou1@hisilicon.com;
> jiangkunkun@huawei.com; zhangfei.gao@linaro.org;
> zhenzhong.duan@intel.com; yi.l.liu@intel.com; Krishnakant Jaju
> <kjaju@nvidia.com>
> Subject: Re: [PATCH v8 00/37] hw/arm/virt: Add support for user-creatable
> accelerated SMMUv3
> 
> On Fri, 23 Jan 2026 at 15:33, Shameer Kolothum
> <skolothumtho@nvidia.com> wrote:
> > > stderr:
> > > acpi-test: Warning! IORT binary file mismatch. Actual
> > > [aml:/tmp/aml-7QQVJ3], Expected
> > > [aml:tests/data/acpi/aarch64/virt/IORT.its_off].
> >
> > Any way to retrieve these files?
> 
> They aren't in the "job artifacts", but you can probably do
> a patch to tweak the CI job to add them, push to your own
> gitlab fork of QEMU to have it run the CI, and then look at
> the results.

I forked your QEMU GitLab repo and pushed my series here:

https://gitlab.com/shamiali2008/qemu/-/commits/target-arm.next-smmuv3-accel

However, I am not seeing any CI jobs running on my fork. In the settings it
shows no assigned runners under Settings CI/CD/Runners, so it looks like
CI is not enabled.

TBH, I am not very familiar with GitLab CI, so I may be missing something
obvious. I will have another look at the settings...

Thanks,
Shameer

On Fri, 23 Jan 2026 at 16:59, Shameer Kolothum <skolothumtho@nvidia.com> wrote:
>
>
>
> > -----Original Message-----
> > From: Peter Maydell <peter.maydell@linaro.org>
> > Sent: 23 January 2026 15:48
> > To: Shameer Kolothum <skolothumtho@nvidia.com>
> > Cc: Jonathan Cameron <jonathan.cameron@huawei.com>; Eric Auger
> > <eric.auger@redhat.com>; qemu-arm@nongnu.org; qemu-
> > devel@nongnu.org; Richard Henderson <richard.henderson@linaro.org>;
> > Jason Gunthorpe <jgg@nvidia.com>; Nicolin Chen <nicolinc@nvidia.com>;
> > ddutile@redhat.com; berrange@redhat.com; clg@redhat.com;
> > alex@shazbot.org; Nathan Chen <nathanc@nvidia.com>; Matt Ochs
> > <mochs@nvidia.com>; smostafa@google.com; wangzhou1@hisilicon.com;
> > jiangkunkun@huawei.com; zhangfei.gao@linaro.org;
> > zhenzhong.duan@intel.com; yi.l.liu@intel.com; Krishnakant Jaju
> > <kjaju@nvidia.com>
> > Subject: Re: [PATCH v8 00/37] hw/arm/virt: Add support for user-creatable
> > accelerated SMMUv3
> >
> > On Fri, 23 Jan 2026 at 15:33, Shameer Kolothum
> > <skolothumtho@nvidia.com> wrote:
> > > > stderr:
> > > > acpi-test: Warning! IORT binary file mismatch. Actual
> > > > [aml:/tmp/aml-7QQVJ3], Expected
> > > > [aml:tests/data/acpi/aarch64/virt/IORT.its_off].
> > >
> > > Any way to retrieve these files?
> >
> > They aren't in the "job artifacts", but you can probably do
> > a patch to tweak the CI job to add them, push to your own
> > gitlab fork of QEMU to have it run the CI, and then look at
> > the results.
>
> I forked your QEMU GitLab repo and pushed my series here:
>
> https://gitlab.com/shamiali2008/qemu/-/commits/target-arm.next-smmuv3-accel
>
> However, I am not seeing any CI jobs running on my fork. In the settings it
> shows no assigned runners under Settings CI/CD/Runners, so it looks like
> CI is not enabled.

You don't need to fork my repo, you can fork the upstream
QEMU one. Things aren't set up to run CI by default because
it would use up your gitlab CI quota. The docs on how to
do this are here:
https://www.qemu.org/docs/master/devel/testing/ci.html
-- you want to push it with the QEMU_CI=1 or =2 settings
to get it to run the CI. The docs suggest a git alias
that you can use to make this simpler.

-- PMM

> -----Original Message-----
> From: Peter Maydell <peter.maydell@linaro.org>
> Sent: 23 January 2026 17:12
> To: Shameer Kolothum <skolothumtho@nvidia.com>
> Cc: Jonathan Cameron <jonathan.cameron@huawei.com>; Eric Auger
> <eric.auger@redhat.com>; qemu-arm@nongnu.org; qemu-
> devel@nongnu.org; Richard Henderson <richard.henderson@linaro.org>;
> Jason Gunthorpe <jgg@nvidia.com>; Nicolin Chen <nicolinc@nvidia.com>;
> ddutile@redhat.com; berrange@redhat.com; clg@redhat.com;
> alex@shazbot.org; Nathan Chen <nathanc@nvidia.com>; Matt Ochs
> <mochs@nvidia.com>; smostafa@google.com; wangzhou1@hisilicon.com;
> jiangkunkun@huawei.com; zhangfei.gao@linaro.org;
> zhenzhong.duan@intel.com; yi.l.liu@intel.com; Krishnakant Jaju
> <kjaju@nvidia.com>
> Subject: Re: [PATCH v8 00/37] hw/arm/virt: Add support for user-creatable
> accelerated SMMUv3
> 
> External email: Use caution opening links or attachments
> 
> 
> On Fri, 23 Jan 2026 at 16:59, Shameer Kolothum
> <skolothumtho@nvidia.com> wrote:
> >
> >
> >
> > > -----Original Message-----
> > > From: Peter Maydell <peter.maydell@linaro.org>
> > > Sent: 23 January 2026 15:48
> > > To: Shameer Kolothum <skolothumtho@nvidia.com>
> > > Cc: Jonathan Cameron <jonathan.cameron@huawei.com>; Eric Auger
> > > <eric.auger@redhat.com>; qemu-arm@nongnu.org; qemu-
> > > devel@nongnu.org; Richard Henderson <richard.henderson@linaro.org>;
> > > Jason Gunthorpe <jgg@nvidia.com>; Nicolin Chen
> > > <nicolinc@nvidia.com>; ddutile@redhat.com; berrange@redhat.com;
> > > clg@redhat.com; alex@shazbot.org; Nathan Chen <nathanc@nvidia.com>;
> > > Matt Ochs <mochs@nvidia.com>; smostafa@google.com;
> > > wangzhou1@hisilicon.com; jiangkunkun@huawei.com;
> > > zhangfei.gao@linaro.org; zhenzhong.duan@intel.com;
> > > yi.l.liu@intel.com; Krishnakant Jaju <kjaju@nvidia.com>
> > > Subject: Re: [PATCH v8 00/37] hw/arm/virt: Add support for
> > > user-creatable accelerated SMMUv3
> > >
> > > On Fri, 23 Jan 2026 at 15:33, Shameer Kolothum
> > > <skolothumtho@nvidia.com> wrote:
> > > > > stderr:
> > > > > acpi-test: Warning! IORT binary file mismatch. Actual
> > > > > [aml:/tmp/aml-7QQVJ3], Expected
> > > > > [aml:tests/data/acpi/aarch64/virt/IORT.its_off].
> > > >
> > > > Any way to retrieve these files?
> > >
> > > They aren't in the "job artifacts", but you can probably do a patch
> > > to tweak the CI job to add them, push to your own gitlab fork of
> > > QEMU to have it run the CI, and then look at the results.
> >
> > I forked your QEMU GitLab repo and pushed my series here:
> >
> > https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fgitl
> > ab.com%2Fshamiali2008%2Fqemu%2F-%2Fcommits%2Ftarget-arm.next-
> smmuv3-ac
> >
> cel&data=05%7C02%7Cskolothumtho%40nvidia.com%7Cc2d80db53d1c4e4
> 28abf08d
> >
> e5aa29cbd%7C43083d15727340c1b7db39efd9ccc17a%7C0%7C0%7C6390
> 47851647858
> >
> 489%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUsIlYiOiIw
> LjAuMDAwMC
> >
> IsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3D%7C0%7C%7C%7C&
> sdata=
> >
> ECtYwLUw5TDXOo%2BHzs4ZdGIfogVqgyPx%2BPKYxJUXF4o%3D&reserved=0
> >
> > However, I am not seeing any CI jobs running on my fork. In the
> > settings it shows no assigned runners under Settings CI/CD/Runners, so
> > it looks like CI is not enabled.
> 
> You don't need to fork my repo, you can fork the upstream QEMU one. Things
> aren't set up to run CI by default because it would use up your gitlab CI quota.
> The docs on how to do this are here:
> https://nam11.safelinks.protection.outlook.com/?url=https%3A%2F%2Fww
> w.qemu.org%2Fdocs%2Fmaster%2Fdevel%2Ftesting%2Fci.html&data=05%7
> C02%7Cskolothumtho%40nvidia.com%7Cc2d80db53d1c4e428abf08de5aa2
> 9cbd%7C43083d15727340c1b7db39efd9ccc17a%7C0%7C0%7C639047851
> 647877924%7CUnknown%7CTWFpbGZsb3d8eyJFbXB0eU1hcGkiOnRydWUs
> IlYiOiIwLjAuMDAwMCIsIlAiOiJXaW4zMiIsIkFOIjoiTWFpbCIsIldUIjoyfQ%3D%3
> D%7C0%7C%7C%7C&sdata=mC973PIuQ5lHxwu3Y19%2BYvOy0lkfWLGk6ejs
> fRkwJXo%3D&reserved=0
> -- you want to push it with the QEMU_CI=1 or =2 settings to get it to run the
> CI. The docs suggest a git alias that you can use to make this simpler.
> 

Thanks Peter, and appreciate the patience and pointers.

I deleted the earlier forks and created a fresh one directly
from upstream QEMU. I cloned it locally and created a branch
with the accel patches, and:

git push -o ci.variable="QEMU_CI=2" origin master-smmuv3-accel-v8

I tried QEMU_CI=1 as well.

However, I’m still not seeing any CI jobs or pipelines show up.
I may be missing something obvious here and will have another
look over the weekend if possible.

Would appreciate it if anyone else familiar with the GitLab CI
setup could take a look, if possible, try to reproduce this, and
help get the IORT files in play here.

Thanks,
Shameer


 

> -----Original Message-----
> From: Shameer Kolothum <skolothumtho@nvidia.com>
> Sent: 23 January 2026 18:23
> To: Peter Maydell <peter.maydell@linaro.org>
> Cc: Jonathan Cameron <jonathan.cameron@huawei.com>; Eric Auger
> <eric.auger@redhat.com>; qemu-arm@nongnu.org; qemu-
> devel@nongnu.org; Richard Henderson <richard.henderson@linaro.org>;
> Jason Gunthorpe <jgg@nvidia.com>; Nicolin Chen <nicolinc@nvidia.com>;
> ddutile@redhat.com; berrange@redhat.com; clg@redhat.com;
> alex@shazbot.org; Nathan Chen <nathanc@nvidia.com>; Matt Ochs
> <mochs@nvidia.com>; smostafa@google.com; wangzhou1@hisilicon.com;
> jiangkunkun@huawei.com; zhangfei.gao@linaro.org;
> zhenzhong.duan@intel.com; yi.l.liu@intel.com; Krishnakant Jaju
> <kjaju@nvidia.com>
> Subject: RE: [PATCH v8 00/37] hw/arm/virt: Add support for user-creatable
> accelerated SMMUv3
> 
> 
 
> Thanks Peter, and appreciate the patience and pointers.

Ok. I manged to trigger the CI jobs.
 
> I deleted the earlier forks and created a fresh one directly
> from upstream QEMU. I cloned it locally and created a branch
> with the accel patches, and:
> 
> git push -o ci.variable="QEMU_CI=2" origin master-smmuv3-accel-v8
> 
> I tried QEMU_CI=1 as well.
> 
> However, I’m still not seeing any CI jobs or pipelines show up.
> I may be missing something obvious here and will have another
> look over the weekend if possible.

I was missing the:

Settings --> CI/CD --> Runners --> Variables --> Minimum role to use
pipeline variables

The above was set to None. Changing it to "Owner" fixed the issue
and CI started working.

And to copy the /tmp/aml-* file, changed:

diff --git a/.gitlab-ci.d/buildtest.yml b/.gitlab-ci.d/buildtest.yml
index e9b5b05e6e..73c5e36ec3 100644
--- a/.gitlab-ci.d/buildtest.yml
+++ b/.gitlab-ci.d/buildtest.yml
@@ -288,6 +288,14 @@ check-system-opensuse:
   variables:
     IMAGE: opensuse-leap
     MAKE_CHECK_ARGS: check
+  after_script:
+    - mkdir -p aml-debug-files
+    - cp /tmp/aml-* aml-debug-files/ || true
+  artifacts:
+    when: always
+    paths:
+      - aml-debug-files/
+    expire_in: 2 days

The generated IORT and the IORT.its_off reference were indeed 
different, with ATS and RMR present. It shouldn’t have either of
those as it is using the legacy-smmuv3.

The issue was not initialising the AcpiIortSMMUv3Dev sdev in
virt-acpi-build.c.

With the below fix,

diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c
index 60d8fda755..9126aae346 100644
--- a/hw/arm/virt-acpi-build.c
+++ b/hw/arm/virt-acpi-build.c
@@ -356,7 +356,7 @@ typedef struct AcpiIortSMMUv3Dev {
 static int populate_smmuv3_legacy_dev(GArray *sdev_blob)
 {
     VirtMachineState *vms = VIRT_MACHINE(qdev_get_machine());
-    AcpiIortSMMUv3Dev sdev;
+    AcpiIortSMMUv3Dev sdev = { 0 };

     sdev.rc_smmu_idmaps = g_array_new(false, true, sizeof(AcpiIortIdMapping));
     object_child_foreach_recursive(object_get_root(), iort_host_bridges,
@@ -391,7 +391,7 @@ static int iort_smmuv3_devices(Object *obj, void *opaque)
     GArray *sdev_blob = opaque;
     AcpiIortIdMapping idmap;
     PlatformBusDevice *pbus;
-    AcpiIortSMMUv3Dev sdev;
+    AcpiIortSMMUv3Dev sdev = { 0 };
     int min_bus, max_bus;
     SysBusDevice *sbdev;
     PCIBus *bus;

The CI test is now successful.
...
  1/457 qemu:qtest+qtest-x86_64 / qtest-x86_64/bios-tables-test              OK              83.38s   55 subtests passed
  2/457 qemu:qtest+qtest-aarch64 / qtest-aarch64/bios-tables-test            OK              89.71s   14 subtests passed
  3/457 qemu:qtest+qtest-s390x / qtest-s390x/qom-test                        OK               0.90s   3 subtests passed
...

I will respin this as v9.

Thanks,
Shameer