32-bit TCG opcodes produced for the i386 target usually looks the same
as 64-bit TCG opcodes produced for the x86_64.  The special one that
needs extensions is 32-bit TCG opcodes produced for the x86_64 target.
Make all #ifdefs look the same, like this:

    case MO_32:
  #ifdef TARGET_X86_64
      /* code using 32-bit opcodes */

    case MO_64:
  #endif
      /* code using target_long opcodes */

  default:
    g_assert_not_reached();

Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
---
 target/i386/tcg/translate.c | 11 ++++++-----
 target/i386/tcg/emit.c.inc  | 18 ++++++++++++------
 2 files changed, 18 insertions(+), 11 deletions(-)

diff --git a/target/i386/tcg/translate.c b/target/i386/tcg/translate.c
index 20aa94347b0..7186517239c 100644
--- a/target/i386/tcg/translate.c
+++ b/target/i386/tcg/translate.c
@@ -430,17 +430,15 @@ static TCGv gen_op_deposit_reg_v(DisasContext *s, MemOp ot, int reg, TCGv dest,
         tcg_gen_deposit_tl(dest, cpu_regs[reg], t0, 0, 16);
         break;
     case MO_32:
-        /* For x86_64, this sets the higher half of register to zero.
-           For i386, this is equivalent to a mov. */
+#ifdef TARGET_X86_64
         dest = dest ? dest : cpu_regs[reg];
         tcg_gen_ext32u_tl(dest, t0);
         break;
-#ifdef TARGET_X86_64
     case MO_64:
+#endif
         dest = dest ? dest : cpu_regs[reg];
         tcg_gen_mov_tl(dest, t0);
         break;
-#endif
     default:
         g_assert_not_reached();
     }
@@ -1585,8 +1583,8 @@ static TCGv gen_shiftd_rm_T1(DisasContext *s, MemOp ot,
             tcg_gen_shri_i64(s->T0, s->T0, 32);
         }
         break;
+    case MO_64:
 #endif
-    default:
         hishift = tcg_temp_new();
         tcg_gen_subi_tl(tmp, count, 1);
         if (is_right) {
@@ -1615,6 +1613,9 @@ static TCGv gen_shiftd_rm_T1(DisasContext *s, MemOp ot,
                            tcg_constant_tl(0), s->T1);
         tcg_gen_or_tl(s->T0, s->T0, s->T1);
         break;
+
+    default:
+        g_assert_not_reached();
     }
 
     return cc_src;
diff --git a/target/i386/tcg/emit.c.inc b/target/i386/tcg/emit.c.inc
index f5f12e48b77..ca0ee4d630d 100644
--- a/target/i386/tcg/emit.c.inc
+++ b/target/i386/tcg/emit.c.inc
@@ -1236,8 +1236,8 @@ static void gen_ADCOX(DisasContext *s, X86DecodedInsn *decode, int cc_op)
     }
 
     switch (ot) {
-#ifdef TARGET_X86_64
     case MO_32:
+#ifdef TARGET_X86_64
         /* If TL is 64-bit just do everything in 64-bit arithmetic.  */
         tcg_gen_ext32u_tl(s->T0, s->T0);
         tcg_gen_ext32u_tl(s->T1, s->T1);
@@ -1245,12 +1245,16 @@ static void gen_ADCOX(DisasContext *s, X86DecodedInsn *decode, int cc_op)
         tcg_gen_add_i64(s->T0, s->T0, carry_in);
         tcg_gen_shri_i64(*carry_out, s->T0, 32);
         break;
+
+    case MO_64:
 #endif
-    default:
         zero = tcg_constant_tl(0);
         tcg_gen_add2_tl(s->T0, *carry_out, s->T0, zero, carry_in, zero);
         tcg_gen_add2_tl(s->T0, *carry_out, s->T0, *carry_out, s->T1, zero);
         break;
+
+    default:
+        g_assert_not_reached();
     }
 }
 
@@ -1991,7 +1995,6 @@ static void gen_DIV(DisasContext *s, X86DecodedInsn *decode)
     case MO_16:
         gen_helper_divw_AX(tcg_env, s->T0);
         break;
-    default:
     case MO_32:
         gen_helper_divl_EAX(tcg_env, s->T0);
         break;
@@ -2000,6 +2003,8 @@ static void gen_DIV(DisasContext *s, X86DecodedInsn *decode)
         gen_helper_divq_EAX(tcg_env, s->T0);
         break;
 #endif
+    default:
+        g_assert_not_reached();
     }
 }
 
@@ -2065,7 +2070,6 @@ static void gen_IDIV(DisasContext *s, X86DecodedInsn *decode)
     case MO_16:
         gen_helper_idivw_AX(tcg_env, s->T0);
         break;
-    default:
     case MO_32:
         gen_helper_idivl_EAX(tcg_env, s->T0);
         break;
@@ -2074,6 +2078,8 @@ static void gen_IDIV(DisasContext *s, X86DecodedInsn *decode)
         gen_helper_idivq_EAX(tcg_env, s->T0);
         break;
 #endif
+    default:
+        g_assert_not_reached();
     }
 }
 
@@ -2895,7 +2901,7 @@ static inline void gen_pextr(DisasContext *s, X86DecodedInsn *decode, MemOp ot)
         tcg_gen_ld_tl(s->T0, tcg_env, vector_elem_offset(&decode->op[1], ot, val));
         break;
     default:
-        abort();
+        g_assert_not_reached();
     }
 }
 
@@ -2942,7 +2948,7 @@ static inline void gen_pinsr(DisasContext *s, X86DecodedInsn *decode, MemOp ot)
         tcg_gen_st_tl(s->T1, tcg_env, vector_elem_offset(&decode->op[0], ot, val));
         break;
     default:
-        abort();
+        g_assert_not_reached();
     }
 }
 
-- 
2.52.0

On 1/15/26 22:33, Paolo Bonzini wrote:
> 32-bit TCG opcodes produced for the i386 target usually looks the same
> as 64-bit TCG opcodes produced for the x86_64.  The special one that
> needs extensions is 32-bit TCG opcodes produced for the x86_64 target.
> Make all #ifdefs look the same, like this:
> 
>      case MO_32:
>    #ifdef TARGET_X86_64
>        /* code using 32-bit opcodes */
> 
>      case MO_64:
>    #endif
>        /* code using target_long opcodes */
> 
>    default:
>      g_assert_not_reached();
> 
> Signed-off-by: Paolo Bonzini <pbonzini@redhat.com>
> ---
>   target/i386/tcg/translate.c | 11 ++++++-----
>   target/i386/tcg/emit.c.inc  | 18 ++++++++++++------
>   2 files changed, 18 insertions(+), 11 deletions(-)

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>


>       case MO_32:
> -        /* For x86_64, this sets the higher half of register to zero.
> -           For i386, this is equivalent to a mov. */
> +#ifdef TARGET_X86_64
>           dest = dest ? dest : cpu_regs[reg];
>           tcg_gen_ext32u_tl(dest, t0);
>           break;
> -#ifdef TARGET_X86_64
>       case MO_64:
> +#endif
>           dest = dest ? dest : cpu_regs[reg];
>           tcg_gen_mov_tl(dest, t0);
>           break;
> -#endif
>       default:
>           g_assert_not_reached();
>       }

This could plausibly share the dest selection code and then use

   tcg_gen_ext_tl(dest, t0, mop).

> @@ -1236,8 +1236,8 @@ static void gen_ADCOX(DisasContext *s, X86DecodedInsn *decode, int cc_op)
...
> +    case MO_64:
>   #endif
> -    default:
>           zero = tcg_constant_tl(0);
>           tcg_gen_add2_tl(s->T0, *carry_out, s->T0, zero, carry_in, zero);
>           tcg_gen_add2_tl(s->T0, *carry_out, s->T0, *carry_out, s->T1, zero);
>           break;

A fairly new function, but this could use

   tcg_gen_addcio_tl(s->T0, *carry_out, s->T0, s->T1, carry_in);


r~