Similarly to the last patch, mcontrol/mcontrol6 trigger types may
not implement the same read/write/execute match capability. Add
configuration to describe what access type matches are supported.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 target/riscv/cpu.c   |  1 +
 target/riscv/debug.c | 26 ++++++++++++++++++++------
 target/riscv/debug.h |  1 +
 3 files changed, 22 insertions(+), 6 deletions(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 5708da5054..d349457c87 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -2967,6 +2967,7 @@ static const RISCVSdtrigConfig default_sdtrig_config = {
                          (1 << TRIGGER_TYPE_AD_MATCH6) |
                          (1 << TRIGGER_TYPE_INST_CNT) |
                          (1 << TRIGGER_TYPE_UNAVAIL),
+            .mcontrol_rwx_mask = 0x7, /* WP/BP */
         },
     },
 };
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index e8d343bf42..d7c171736f 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -449,7 +449,11 @@ static inline bool type2_breakpoint_enabled(target_ulong ctrl)
 static target_ulong type2_mcontrol_validate(CPURISCVState *env,
                                             target_ulong ctrl)
 {
+    CPUState *cs = env_cpu(env);
+    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
+    target_ulong index = env->sdtrig_state.trigger_cur;
     target_ulong val;
+    target_ulong rwx_mask;
     uint32_t size;
 
     /* validate the generic part first */
@@ -475,9 +479,12 @@ static target_ulong type2_mcontrol_validate(CPURISCVState *env,
         }
     }
 
-    /* keep the mode and attribute bits */
-    val |= (ctrl & (TYPE2_U | TYPE2_S | TYPE2_M |
-                    TYPE2_LOAD | TYPE2_STORE | TYPE2_EXEC));
+    /* only set supported access (load/store/exec) bits */
+    rwx_mask = mcc->def->debug_cfg->triggers[index].mcontrol_rwx_mask;
+    val |= ctrl & rwx_mask;
+
+    /* keep the mode bits */
+    val |= ctrl & (TYPE2_U | TYPE2_S | TYPE2_M);
 
     return val;
 }
@@ -573,7 +580,11 @@ static inline bool type6_breakpoint_enabled(target_ulong ctrl)
 static target_ulong type6_mcontrol6_validate(CPURISCVState *env,
                                              target_ulong ctrl)
 {
+    CPUState *cs = env_cpu(env);
+    RISCVCPUClass *mcc = RISCV_CPU_GET_CLASS(cs);
+    target_ulong index = env->sdtrig_state.trigger_cur;
     target_ulong val;
+    target_ulong rwx_mask;
     uint32_t size;
 
     /* validate the generic part first */
@@ -596,9 +607,12 @@ static target_ulong type6_mcontrol6_validate(CPURISCVState *env,
         val |= (ctrl & TYPE6_SIZE);
     }
 
-    /* keep the mode and attribute bits */
-    val |= (ctrl & (TYPE6_VU | TYPE6_VS | TYPE6_U | TYPE6_S | TYPE6_M |
-                    TYPE6_LOAD | TYPE6_STORE | TYPE6_EXEC));
+    /* only set supported access (load/store/exec) bits */
+    rwx_mask = mcc->def->debug_cfg->triggers[index].mcontrol_rwx_mask;
+    val |= ctrl & rwx_mask;
+
+    /* keep the mode bits */
+    val |= (ctrl & (TYPE6_VU | TYPE6_VS | TYPE6_U | TYPE6_S | TYPE6_M));
 
     return val;
 }
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
index f9e840d615..c9f7225954 100644
--- a/target/riscv/debug.h
+++ b/target/riscv/debug.h
@@ -137,6 +137,7 @@ enum {
 
 struct trigger_properties {
     uint16_t type_mask; /* Trigger types supported (0 = no trigger here) */
+    uint8_t mcontrol_rwx_mask; /* mc/mc6 rwx access match supported */
 };
 
 typedef struct RISCVSdtrigConfig {
-- 
2.51.0