No need for machine.c to know internals of how debug.c maintains debug
state.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
---
 target/riscv/debug.c   | 9 ++++++++-
 target/riscv/debug.h   | 2 +-
 target/riscv/machine.c | 4 +---
 3 files changed, 10 insertions(+), 5 deletions(-)

diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 973de3b2e2..24161fd46b 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -673,7 +673,7 @@ static bool check_itrigger_priv(CPURISCVState *env, int index)
     return icount_priv_match(env, index);
 }
 
-bool riscv_itrigger_enabled(CPURISCVState *env)
+static bool riscv_itrigger_enabled(CPURISCVState *env)
 {
     int count;
 
@@ -1124,6 +1124,13 @@ void riscv_cpu_debug_change_priv(CPURISCVState *env)
     }
 }
 
+void riscv_cpu_debug_post_load(CPURISCVState *env)
+{
+    if (!icount_enabled()) {
+        env->itrigger_enabled = riscv_itrigger_enabled(env);
+    }
+}
+
 void riscv_trigger_reset_hold(CPURISCVState *env)
 {
     target_ulong tdata1 = build_tdata1(env, TRIGGER_TYPE_AD_MATCH, 0, 0);
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
index 5a14b7894e..400c023943 100644
--- a/target/riscv/debug.h
+++ b/target/riscv/debug.h
@@ -151,9 +151,9 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
 void riscv_trigger_realize(CPURISCVState *env);
 void riscv_trigger_reset_hold(CPURISCVState *env);
 
-bool riscv_itrigger_enabled(CPURISCVState *env);
 void riscv_itrigger_update_priv(CPURISCVState *env);
 
 void riscv_cpu_debug_change_priv(CPURISCVState *env);
+void riscv_cpu_debug_post_load(CPURISCVState *env);
 
 #endif /* RISCV_DEBUG_H */
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 34fd73c920..bee1445a31 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -230,9 +230,7 @@ static int debug_post_load(void *opaque, int version_id)
     RISCVCPU *cpu = opaque;
     CPURISCVState *env = &cpu->env;
 
-    if (!icount_enabled()) {
-        env->itrigger_enabled = riscv_itrigger_enabled(env);
-    }
+    riscv_cpu_debug_post_load(env);
 
     return 0;
 }
-- 
2.51.0