Add missing return statement after logging the error when cs is NULL.

Resolves: Coverity CID 1644077

Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
---
 target/riscv/cpu.c | 1 +
 1 file changed, 1 insertion(+)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 3b9d17d58d..10ece4bf63 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -83,6 +83,7 @@ void cpu_set_exception_base(int vp_index, target_ulong address)
         qemu_log_mask(LOG_GUEST_ERROR,
                       "cpu_set_exception_base: invalid vp_index: %u",
                       vp_index);
+        return;
     }
     cpu = RISCV_CPU(cs);
     cpu->env.resetvec = address;
-- 
2.34.1

On Mon, Jan 12, 2026 at 7:05 PM Djordje Todorovic
<Djordje.Todorovic@htecgroup.com> wrote:
>
> Add missing return statement after logging the error when cs is NULL.
>
> Resolves: Coverity CID 1644077
>
> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>

Reviewed-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

> ---
>  target/riscv/cpu.c | 1 +
>  1 file changed, 1 insertion(+)
>
> diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
> index 3b9d17d58d..10ece4bf63 100644
> --- a/target/riscv/cpu.c
> +++ b/target/riscv/cpu.c
> @@ -83,6 +83,7 @@ void cpu_set_exception_base(int vp_index, target_ulong address)
>          qemu_log_mask(LOG_GUEST_ERROR,
>                        "cpu_set_exception_base: invalid vp_index: %u",
>                        vp_index);
> +        return;
>      }
>      cpu = RISCV_CPU(cs);
>      cpu->env.resetvec = address;
> --
> 2.34.1

On 12/1/26 10:05, Djordje Todorovic wrote:
> Add missing return statement after logging the error when cs is NULL.
> 
> Resolves: Coverity CID 1644077
> 

Fixes: 209c2c9af62 ("target/riscv: Add cpu_set_exception_base")

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>


> Signed-off-by: Djordje Todorovic <djordje.todorovic@htecgroup.com>
> ---
>   target/riscv/cpu.c | 1 +
>   1 file changed, 1 insertion(+)