With TARGET_ADDRESS_BITS mechanism, it's now possible to specify which
variant every source file is written for. Compared to before, it means
that addr_type will now vary per tb translation, where it was constant
for a given target previously.

Instead of introducing a new parameter to translator_loop(), we simply
add this information in TCGTBCPUState, which is returned by
get_tb_cpu_state() during the translation, and passed down to
tb_gen_code().

To avoid modifying all target with this new field, we simply define a
default value that is equivalent to current state: use
target_long_bits(). With this, we can progressively convert new
architectures.

Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
---
 include/accel/tcg/tb-cpu-state.h | 12 ++++++++++++
 accel/tcg/translate-all.c        | 15 ++++++++++++++-
 2 files changed, 26 insertions(+), 1 deletion(-)

diff --git a/include/accel/tcg/tb-cpu-state.h b/include/accel/tcg/tb-cpu-state.h
index 8f912900ca6..b77c4dd5100 100644
--- a/include/accel/tcg/tb-cpu-state.h
+++ b/include/accel/tcg/tb-cpu-state.h
@@ -8,11 +8,23 @@
 
 #include "exec/vaddr.h"
 
+/*
+ * Default value 0 means to refer to target_long_bits(). It allows to stay
+ * compatible with architectures that don't yet have varying definition of TCGv
+ * depending on execution mode.
+ */
+typedef enum TCGvType {
+    TCGV_TYPE_TARGET_LONG = 0,
+    TCGV_TYPE_I32,
+    TCGV_TYPE_I64,
+} TCGvType;
+
 typedef struct TCGTBCPUState {
     vaddr pc;
     uint32_t flags;
     uint32_t cflags;
     uint64_t cs_base;
+    TCGvType tcgv_type;
 } TCGTBCPUState;
 
 #endif
diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
index fba4e9dc21c..bc5d9d74e21 100644
--- a/accel/tcg/translate-all.c
+++ b/accel/tcg/translate-all.c
@@ -257,6 +257,19 @@ static int setjmp_gen_code(CPUArchState *env, TranslationBlock *tb,
     return tcg_gen_code(tcg_ctx, tb, pc);
 }
 
+static TCGType tcgv_type_to_tcg_type(TCGvType t)
+{
+    switch (t) {
+    case TCGV_TYPE_TARGET_LONG:
+        return target_long_bits() == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
+    case TCGV_TYPE_I32:
+        return TCG_TYPE_I32;
+    case TCGV_TYPE_I64:
+        return TCG_TYPE_I64;
+    }
+    g_assert_not_reached();
+}
+
 /* Called with mmap_lock held for user mode emulation.  */
 TranslationBlock *tb_gen_code(CPUState *cpu, TCGTBCPUState s)
 {
@@ -316,7 +329,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, TCGTBCPUState s)
     }
 
     tcg_ctx->gen_tb = tb;
-    tcg_ctx->addr_type = target_long_bits() == 32 ? TCG_TYPE_I32 : TCG_TYPE_I64;
+    tcg_ctx->addr_type = tcgv_type_to_tcg_type(s.tcgv_type);
     tcg_ctx->guest_mo = cpu->cc->tcg_ops->guest_default_memory_order;
 
  restart_translate:
-- 
2.47.3

On 1/9/26 16:31, Pierrick Bouvier wrote:
> With TARGET_ADDRESS_BITS mechanism, it's now possible to specify which
> variant every source file is written for. Compared to before, it means
> that addr_type will now vary per tb translation, where it was constant
> for a given target previously.
> 
> Instead of introducing a new parameter to translator_loop(), we simply
> add this information in TCGTBCPUState, which is returned by
> get_tb_cpu_state() during the translation, and passed down to
> tb_gen_code().
> 
> To avoid modifying all target with this new field, we simply define a
> default value that is equivalent to current state: use
> target_long_bits(). With this, we can progressively convert new
> architectures.
> 
> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> ---
>   include/accel/tcg/tb-cpu-state.h | 12 ++++++++++++
>   accel/tcg/translate-all.c        | 15 ++++++++++++++-
>   2 files changed, 26 insertions(+), 1 deletion(-)
> 
> diff --git a/include/accel/tcg/tb-cpu-state.h b/include/accel/tcg/tb-cpu-state.h
> index 8f912900ca6..b77c4dd5100 100644
> --- a/include/accel/tcg/tb-cpu-state.h
> +++ b/include/accel/tcg/tb-cpu-state.h
> @@ -8,11 +8,23 @@
>   
>   #include "exec/vaddr.h"
>   
> +/*
> + * Default value 0 means to refer to target_long_bits(). It allows to stay
> + * compatible with architectures that don't yet have varying definition of TCGv
> + * depending on execution mode.
> + */
> +typedef enum TCGvType {
> +    TCGV_TYPE_TARGET_LONG = 0,
> +    TCGV_TYPE_I32,
> +    TCGV_TYPE_I64,
> +} TCGvType;
> +
>   typedef struct TCGTBCPUState {
>       vaddr pc;
>       uint32_t flags;
>       uint32_t cflags;
>       uint64_t cs_base;
> +    TCGvType tcgv_type;
>   } TCGTBCPUState;

No need for this.  This state is already present in flags, in a target-specific manner. 
If you actually needed this information, you'd want a new target hook.  However...

> @@ -316,7 +329,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, TCGTBCPUState s)
>       }
>   
>       tcg_ctx->gen_tb = tb;
> -    tcg_ctx->addr_type = target_long_bits() == 32 ? TCG_TYPE_I32 : TCG_TYPE_I64;
> +    tcg_ctx->addr_type = tcgv_type_to_tcg_type(s.tcgv_type);

I did mention in our discussion that it would be best to set this in translator_loop() 
instead, via a new parameter.

This makes it trivial for target/arm/tcg/translate.c to simply tell us that TCG_TYPE_I32 
is correct, for target/arm/tcg/translate-a64.c to specify TCG_TYPE_I64, and for all other 
users to use TCG_TYPE_TL.


r~

On 1/9/26 2:13 PM, Richard Henderson wrote:
> On 1/9/26 16:31, Pierrick Bouvier wrote:
>> With TARGET_ADDRESS_BITS mechanism, it's now possible to specify which
>> variant every source file is written for. Compared to before, it means
>> that addr_type will now vary per tb translation, where it was constant
>> for a given target previously.
>>
>> Instead of introducing a new parameter to translator_loop(), we simply
>> add this information in TCGTBCPUState, which is returned by
>> get_tb_cpu_state() during the translation, and passed down to
>> tb_gen_code().
>>
>> To avoid modifying all target with this new field, we simply define a
>> default value that is equivalent to current state: use
>> target_long_bits(). With this, we can progressively convert new
>> architectures.
>>
>> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
>> ---
>>    include/accel/tcg/tb-cpu-state.h | 12 ++++++++++++
>>    accel/tcg/translate-all.c        | 15 ++++++++++++++-
>>    2 files changed, 26 insertions(+), 1 deletion(-)
>>
>> diff --git a/include/accel/tcg/tb-cpu-state.h b/include/accel/tcg/tb-cpu-state.h
>> index 8f912900ca6..b77c4dd5100 100644
>> --- a/include/accel/tcg/tb-cpu-state.h
>> +++ b/include/accel/tcg/tb-cpu-state.h
>> @@ -8,11 +8,23 @@
>>    
>>    #include "exec/vaddr.h"
>>    
>> +/*
>> + * Default value 0 means to refer to target_long_bits(). It allows to stay
>> + * compatible with architectures that don't yet have varying definition of TCGv
>> + * depending on execution mode.
>> + */
>> +typedef enum TCGvType {
>> +    TCGV_TYPE_TARGET_LONG = 0,
>> +    TCGV_TYPE_I32,
>> +    TCGV_TYPE_I64,
>> +} TCGvType;
>> +
>>    typedef struct TCGTBCPUState {
>>        vaddr pc;
>>        uint32_t flags;
>>        uint32_t cflags;
>>        uint64_t cs_base;
>> +    TCGvType tcgv_type;
>>    } TCGTBCPUState;
> 
> No need for this.  This state is already present in flags, in a target-specific manner.
> If you actually needed this information, you'd want a new target hook.  However...
> 
>> @@ -316,7 +329,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, TCGTBCPUState s)
>>        }
>>    
>>        tcg_ctx->gen_tb = tb;
>> -    tcg_ctx->addr_type = target_long_bits() == 32 ? TCG_TYPE_I32 : TCG_TYPE_I64;
>> +    tcg_ctx->addr_type = tcgv_type_to_tcg_type(s.tcgv_type);
> 
> I did mention in our discussion that it would be best to set this in translator_loop()
> instead, via a new parameter.
> 

I went through this, and noticed that crossing layers was not really 
better than having it there. TCGTBCPUState looked like the best place 
for it.
Now if you really prefer having a translator_loop parameter, I don't 
mind. It will just need a patch for all existing arch.

> This makes it trivial for target/arm/tcg/translate.c to simply tell us that TCG_TYPE_I32
> is correct, for target/arm/tcg/translate-a64.c to specify TCG_TYPE_I64, and for all other
> users to use TCG_TYPE_TL.
>
> 
> r~

On 1/10/26 09:30, Pierrick Bouvier wrote:
> On 1/9/26 2:13 PM, Richard Henderson wrote:
>> On 1/9/26 16:31, Pierrick Bouvier wrote:
>>> With TARGET_ADDRESS_BITS mechanism, it's now possible to specify which
>>> variant every source file is written for. Compared to before, it means
>>> that addr_type will now vary per tb translation, where it was constant
>>> for a given target previously.
>>>
>>> Instead of introducing a new parameter to translator_loop(), we simply
>>> add this information in TCGTBCPUState, which is returned by
>>> get_tb_cpu_state() during the translation, and passed down to
>>> tb_gen_code().
>>>
>>> To avoid modifying all target with this new field, we simply define a
>>> default value that is equivalent to current state: use
>>> target_long_bits(). With this, we can progressively convert new
>>> architectures.
>>>
>>> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
>>> ---
>>>    include/accel/tcg/tb-cpu-state.h | 12 ++++++++++++
>>>    accel/tcg/translate-all.c        | 15 ++++++++++++++-
>>>    2 files changed, 26 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/include/accel/tcg/tb-cpu-state.h b/include/accel/tcg/tb-cpu-state.h
>>> index 8f912900ca6..b77c4dd5100 100644
>>> --- a/include/accel/tcg/tb-cpu-state.h
>>> +++ b/include/accel/tcg/tb-cpu-state.h
>>> @@ -8,11 +8,23 @@
>>>    #include "exec/vaddr.h"
>>> +/*
>>> + * Default value 0 means to refer to target_long_bits(). It allows to stay
>>> + * compatible with architectures that don't yet have varying definition of TCGv
>>> + * depending on execution mode.
>>> + */
>>> +typedef enum TCGvType {
>>> +    TCGV_TYPE_TARGET_LONG = 0,
>>> +    TCGV_TYPE_I32,
>>> +    TCGV_TYPE_I64,
>>> +} TCGvType;
>>> +
>>>    typedef struct TCGTBCPUState {
>>>        vaddr pc;
>>>        uint32_t flags;
>>>        uint32_t cflags;
>>>        uint64_t cs_base;
>>> +    TCGvType tcgv_type;
>>>    } TCGTBCPUState;
>>
>> No need for this.  This state is already present in flags, in a target-specific manner.
>> If you actually needed this information, you'd want a new target hook.  However...
>>
>>> @@ -316,7 +329,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, TCGTBCPUState s)
>>>        }
>>>        tcg_ctx->gen_tb = tb;
>>> -    tcg_ctx->addr_type = target_long_bits() == 32 ? TCG_TYPE_I32 : TCG_TYPE_I64;
>>> +    tcg_ctx->addr_type = tcgv_type_to_tcg_type(s.tcgv_type);
>>
>> I did mention in our discussion that it would be best to set this in translator_loop()
>> instead, via a new parameter.
>>
> 
> I went through this, and noticed that crossing layers was not really better than having it 
> there. TCGTBCPUState looked like the best place for it.

It really isn't.  TCGTBCPUState is used for TB hashtable lookup.
You've added something to the type that is unrelated.


r~


> Now if you really prefer having a translator_loop parameter, I don't mind. It will just 
> need a patch for all existing arch.
> 
>> This makes it trivial for target/arm/tcg/translate.c to simply tell us that TCG_TYPE_I32
>> is correct, for target/arm/tcg/translate-a64.c to specify TCG_TYPE_I64, and for all other
>> users to use TCG_TYPE_TL.
>>
>>
>> r~
> 

On 1/9/26 06:31, Pierrick Bouvier wrote:
> With TARGET_ADDRESS_BITS mechanism, it's now possible to specify which
> variant every source file is written for. Compared to before, it means
> that addr_type will now vary per tb translation, where it was constant
> for a given target previously.
> 
> Instead of introducing a new parameter to translator_loop(), we simply
> add this information in TCGTBCPUState, which is returned by
> get_tb_cpu_state() during the translation, and passed down to
> tb_gen_code().
> 
> To avoid modifying all target with this new field, we simply define a
> default value that is equivalent to current state: use
> target_long_bits(). With this, we can progressively convert new
> architectures.
> 
> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> ---
>   include/accel/tcg/tb-cpu-state.h | 12 ++++++++++++
>   accel/tcg/translate-all.c        | 15 ++++++++++++++-
>   2 files changed, 26 insertions(+), 1 deletion(-)
> 
> diff --git a/include/accel/tcg/tb-cpu-state.h b/include/accel/tcg/tb-cpu-state.h
> index 8f912900ca6..b77c4dd5100 100644
> --- a/include/accel/tcg/tb-cpu-state.h
> +++ b/include/accel/tcg/tb-cpu-state.h
> @@ -8,11 +8,23 @@
>   
>   #include "exec/vaddr.h"
>   
> +/*
> + * Default value 0 means to refer to target_long_bits(). It allows to stay
> + * compatible with architectures that don't yet have varying definition of TCGv
> + * depending on execution mode.
> + */
> +typedef enum TCGvType {
> +    TCGV_TYPE_TARGET_LONG = 0,
> +    TCGV_TYPE_I32,
> +    TCGV_TYPE_I64,
> +} TCGvType;
> +
>   typedef struct TCGTBCPUState {
>       vaddr pc;
>       uint32_t flags;
>       uint32_t cflags;
>       uint64_t cs_base;
> +    TCGvType tcgv_type;
./
I know you're trying to avoid more treewide changes and focus on arm 
instead; but it would not be hard to make this TCGType already, or at 
least use TCGV_TYPE_TARGET_LONG only for the other four mixed-length 
frontends (i386, riscv, sparc, and x86_64).

Also, please call it addr_type since tcgv_type makes less sense in the 
long run.

Paolo

>   } TCGTBCPUState;
>   
>   #endif
> diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c
> index fba4e9dc21c..bc5d9d74e21 100644
> --- a/accel/tcg/translate-all.c
> +++ b/accel/tcg/translate-all.c
> @@ -257,6 +257,19 @@ static int setjmp_gen_code(CPUArchState *env, TranslationBlock *tb,
>       return tcg_gen_code(tcg_ctx, tb, pc);
>   }
>   
> +static TCGType tcgv_type_to_tcg_type(TCGvType t)
> +{
> +    switch (t) {
> +    case TCGV_TYPE_TARGET_LONG:
> +        return target_long_bits() == 64 ? TCG_TYPE_I64 : TCG_TYPE_I32;
> +    case TCGV_TYPE_I32:
> +        return TCG_TYPE_I32;
> +    case TCGV_TYPE_I64:
> +        return TCG_TYPE_I64;
> +    }
> +    g_assert_not_reached();
> +}
> +
>   /* Called with mmap_lock held for user mode emulation.  */
>   TranslationBlock *tb_gen_code(CPUState *cpu, TCGTBCPUState s)
>   {
> @@ -316,7 +329,7 @@ TranslationBlock *tb_gen_code(CPUState *cpu, TCGTBCPUState s)
>       }
>   
>       tcg_ctx->gen_tb = tb;
> -    tcg_ctx->addr_type = target_long_bits() == 32 ? TCG_TYPE_I32 : TCG_TYPE_I64;
> +    tcg_ctx->addr_type = tcgv_type_to_tcg_type(s.tcgv_type);
>       tcg_ctx->guest_mo = cpu->cc->tcg_ops->guest_default_memory_order;
>   
>    restart_translate:

On 1/9/26 6:23 AM, Paolo Bonzini wrote:
> On 1/9/26 06:31, Pierrick Bouvier wrote:
>> With TARGET_ADDRESS_BITS mechanism, it's now possible to specify which
>> variant every source file is written for. Compared to before, it means
>> that addr_type will now vary per tb translation, where it was constant
>> for a given target previously.
>>
>> Instead of introducing a new parameter to translator_loop(), we simply
>> add this information in TCGTBCPUState, which is returned by
>> get_tb_cpu_state() during the translation, and passed down to
>> tb_gen_code().
>>
>> To avoid modifying all target with this new field, we simply define a
>> default value that is equivalent to current state: use
>> target_long_bits(). With this, we can progressively convert new
>> architectures.
>>
>> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
>> ---
>>    include/accel/tcg/tb-cpu-state.h | 12 ++++++++++++
>>    accel/tcg/translate-all.c        | 15 ++++++++++++++-
>>    2 files changed, 26 insertions(+), 1 deletion(-)
>>
>> diff --git a/include/accel/tcg/tb-cpu-state.h b/include/accel/tcg/tb-cpu-state.h
>> index 8f912900ca6..b77c4dd5100 100644
>> --- a/include/accel/tcg/tb-cpu-state.h
>> +++ b/include/accel/tcg/tb-cpu-state.h
>> @@ -8,11 +8,23 @@
>>    
>>    #include "exec/vaddr.h"
>>    
>> +/*
>> + * Default value 0 means to refer to target_long_bits(). It allows to stay
>> + * compatible with architectures that don't yet have varying definition of TCGv
>> + * depending on execution mode.
>> + */
>> +typedef enum TCGvType {
>> +    TCGV_TYPE_TARGET_LONG = 0,
>> +    TCGV_TYPE_I32,
>> +    TCGV_TYPE_I64,
>> +} TCGvType;
>> +
>>    typedef struct TCGTBCPUState {
>>        vaddr pc;
>>        uint32_t flags;
>>        uint32_t cflags;
>>        uint64_t cs_base;
>> +    TCGvType tcgv_type;
> ./
> I know you're trying to avoid more treewide changes and focus on arm
> instead; but it would not be hard to make this TCGType already, or at
> least use TCGV_TYPE_TARGET_LONG only for the other four mixed-length
> frontends (i386, riscv, sparc, and x86_64).
>

I'm not opposed to do this change, but I was (and am) not sure which 
value should apply to which arch.
Mips and ppc have 32 and 64 bits also.
I would feel safer to start with arm only for now and tag other 
architecture while we continue progressing on the single-binary.

> Also, please call it addr_type since tcgv_type makes less sense in the
> long run.
>

Ok!

> Paolo

Il ven 9 gen 2026, 17:26 Pierrick Bouvier <pierrick.bouvier@linaro.org> ha
scritto:

> > I know you're trying to avoid more treewide changes and focus on arm
> > instead; but it would not be hard to make this TCGType already, or at
> > least use TCGV_TYPE_TARGET_LONG only for the other four mixed-length
> > frontends (i386, riscv, sparc, and x86_64).
> >
>
> I'm not opposed to do this change, but I was (and am) not sure which
> value should apply to which arch.
> Mips and ppc have 32 and 64 bits also.
> I would feel safer to start with arm only for now and tag other
> architecture while we continue progressing on the single-binary.
>

The value corresponding to TARGET_LONG_BITS, i.e. TCG_TYPE_TL, is always
safe to use (though for single-size target it would be cleaner to use the
right one).

> Also, please call it addr_type since tcgv_type makes less sense in the
> > long run.
> >
>
> Ok!
>

Thanks,

Paolo

On 1/9/26 9:45 AM, Paolo Bonzini wrote:
> 
> 
> Il ven 9 gen 2026, 17:26 Pierrick Bouvier <pierrick.bouvier@linaro.org 
> <mailto:pierrick.bouvier@linaro.org>> ha scritto:
> 
>      > I know you're trying to avoid more treewide changes and focus on arm
>      > instead; but it would not be hard to make this TCGType already, or at
>      > least use TCGV_TYPE_TARGET_LONG only for the other four mixed-length
>      > frontends (i386, riscv, sparc, and x86_64).
>      >
> 
>     I'm not opposed to do this change, but I was (and am) not sure which
>     value should apply to which arch.
>     Mips and ppc have 32 and 64 bits also.
>     I would feel safer to start with arm only for now and tag other
>     architecture while we continue progressing on the single-binary.
> 
> 
> The value corresponding to TARGET_LONG_BITS, i.e. TCG_TYPE_TL, is always 
> safe to use (though for single-size target it would be cleaner to use 
> the right one).
>

I'm not sure what was the point you initially mentioned.

TCG_TYPE_TL does not have a constant definition, it's aliases to 
TCG_TYPE_I32 or TCG_TYPE_I64, so we can't use it.

Do you want to see explicitly .addr_type = TCG_ADDR_TYPE_TARGET_LONG 
everywhere (except arm which specialize this), instead of relying on 
default value?
Or do you expect something different?

>      > Also, please call it addr_type since tcgv_type makes less sense
>     in the
>      > long run.
>      >
> 
>     Ok!
> 
> 
> Thanks,
> 
> Paolo

Il ven 9 gen 2026, 19:38 Pierrick Bouvier <pierrick.bouvier@linaro.org> ha
scritto:

> Do you want to see explicitly .addr_type = TCG_ADDR_TYPE_TARGET_LONG
> everywhere (except arm which specialize this), instead of relying on
> default value?
>

That would be one way, but in the get_tb_cpu_state function you *could*
return
.addr_type = TCG_TYPE_TL, even if it's not constant, couldn't you?

Arm would specialize it, but the other targets don't have their
get_tb_cpu_state function in a common file.

Paolo

Or do you expect something different?
>
> >      > Also, please call it addr_type since tcgv_type makes less sense
> >     in the
> >      > long run.
> >      >
> >
> >     Ok!
> >
> >
> > Thanks,
> >
> > Paolo
>
>

On 1/9/26 12:34 PM, Paolo Bonzini wrote:
> 
> 
> Il ven 9 gen 2026, 19:38 Pierrick Bouvier <pierrick.bouvier@linaro.org 
> <mailto:pierrick.bouvier@linaro.org>> ha scritto:
> 
>     Do you want to see explicitly .addr_type = TCG_ADDR_TYPE_TARGET_LONG
>     everywhere (except arm which specialize this), instead of relying on
>     default value?
> 
> 
> That would be one way, but in the get_tb_cpu_state function you *could* 
> return
> .addr_type = TCG_TYPE_TL, even if it's not constant, couldn't you?
> 
> Arm would specialize it, but the other targets don't have their 
> get_tb_cpu_state function in a common file.
>

Ok. That's what is done in patch 29, in case you might have missed it.

> Paolo
> 
>     Or do you expect something different?
> 
>      >      > Also, please call it addr_type since tcgv_type makes less
>     sense
>      >     in the
>      >      > long run.
>      >      >
>      >
>      >     Ok!
>      >
>      >
>      > Thanks,
>      >
>      > Paolo
> 

On 9/1/26 06:31, Pierrick Bouvier wrote:
> With TARGET_ADDRESS_BITS mechanism, it's now possible to specify which
> variant every source file is written for. Compared to before, it means
> that addr_type will now vary per tb translation, where it was constant
> for a given target previously.
> 
> Instead of introducing a new parameter to translator_loop(), we simply
> add this information in TCGTBCPUState, which is returned by
> get_tb_cpu_state() during the translation, and passed down to
> tb_gen_code().
> 
> To avoid modifying all target with this new field, we simply define a
> default value that is equivalent to current state: use
> target_long_bits(). With this, we can progressively convert new
> architectures.
> 
> Signed-off-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>
> ---
>   include/accel/tcg/tb-cpu-state.h | 12 ++++++++++++
>   accel/tcg/translate-all.c        | 15 ++++++++++++++-
>   2 files changed, 26 insertions(+), 1 deletion(-)

Also nice :)

Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>