Remove 32-bit host support

[PATCH 33/50] target/riscv: Drop TCG_TARGET_REG_BITS test

Richard Henderson posted 50 patches 2 days, 5 hours ago

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Maintainers: "Alex Bennée" <alex.bennee@linaro.org>, "Philippe Mathieu-Daudé" <philmd@linaro.org>, Thomas Huth <thuth@redhat.com>, Paolo Bonzini <pbonzini@redhat.com>, Fabiano Rosas <farosas@suse.de>, Laurent Vivier <lvivier@redhat.com>, Richard Henderson <richard.henderson@linaro.org>, Riku Voipio <riku.voipio@iki.fi>, Stefan Hajnoczi <stefanha@redhat.com>, Fam Zheng <fam@euphon.net>, Kevin Wolf <kwolf@redhat.com>, Hanna Reitz <hreitz@redhat.com>, Warner Losh <imp@bsdimp.com>, Kyle Evans <kevans@freebsd.org>, "Daniel P. Berrangé" <berrange@redhat.com>, Stefano Stabellini <sstabellini@kernel.org>, Anthony PERARD <anthony@xenproject.org>, Paul Durrant <paul@xen.org>, "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, "Michael S. Tsirkin" <mst@redhat.com>, David Hildenbrand <david@kernel.org>, "Marc-André Lureau" <marcandre.lureau@redhat.com>, Peter Xu <peterx@redhat.com>, Li Zhijian <lizhijian@fujitsu.com>, Hyman Huang <yong.huang@smartx.com>, Peter Maydell <peter.maydell@linaro.org>, Helge Deller <deller@gmx.de>, Zhao Liu <zhao1.liu@intel.com>, Eduardo Habkost <eduardo@habkost.net>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Ilya Leoshkevich <iii@linux.ibm.com>, WANG Xuerui <git@xen0n.name>, Stefan Weil <sw@weilnetz.de>

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[PATCH 33/50] target/riscv: Drop TCG_TARGET_REG_BITS test

Posted by Richard Henderson 2 days, 5 hours ago

Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
---
 target/riscv/insn_trans/trans_rvv.c.inc | 54 ++++++-------------------
 1 file changed, 13 insertions(+), 41 deletions(-)

diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
index caefd38216..4df9a40b44 100644
--- a/target/riscv/insn_trans/trans_rvv.c.inc
+++ b/target/riscv/insn_trans/trans_rvv.c.inc
@@ -1181,60 +1181,32 @@ static bool ldst_whole_trans(uint32_t vd, uint32_t rs1, uint32_t nf,
      * Update vstart with the number of processed elements.
      * Use the helper function if either:
      * - vstart is not 0.
-     * - the target has 32 bit registers and we are loading/storing 64 bit long
-     *   elements. This is to ensure that we process every element with a single
-     *   memory instruction.
      */
 
-    bool use_helper_fn = !(s->vstart_eq_zero) ||
-                          (TCG_TARGET_REG_BITS == 32 && log2_esz == 3);
+    bool use_helper_fn = !s->vstart_eq_zero;
 
     if (!use_helper_fn) {
-        TCGv addr = tcg_temp_new();
         uint32_t size = s->cfg_ptr->vlenb * nf;
         TCGv_i64 t8 = tcg_temp_new_i64();
-        TCGv_i32 t4 = tcg_temp_new_i32();
         MemOp atomicity = MO_ATOM_NONE;
         if (log2_esz == 0) {
             atomicity = MO_ATOM_NONE;
         } else {
             atomicity = MO_ATOM_IFALIGN_PAIR;
         }
-        if (TCG_TARGET_REG_BITS == 64) {
-            for (int i = 0; i < size; i += 8) {
-                addr = get_address(s, rs1, i);
-                if (is_load) {
-                    tcg_gen_qemu_ld_i64(t8, addr, s->mem_idx,
-                            MO_LE | MO_64 | atomicity);
-                    tcg_gen_st_i64(t8, tcg_env, vreg_ofs(s, vd) + i);
-                } else {
-                    tcg_gen_ld_i64(t8, tcg_env, vreg_ofs(s, vd) + i);
-                    tcg_gen_qemu_st_i64(t8, addr, s->mem_idx,
-                            MO_LE | MO_64 | atomicity);
-                }
-                if (i == size - 8) {
-                    tcg_gen_movi_tl(cpu_vstart, 0);
-                } else {
-                    tcg_gen_addi_tl(cpu_vstart, cpu_vstart, 8 >> log2_esz);
-                }
+        for (int i = 0; i < size; i += 8) {
+            TCGv addr = get_address(s, rs1, i);
+            if (is_load) {
+                tcg_gen_qemu_ld_i64(t8, addr, s->mem_idx, MO_LEUQ | atomicity);
+                tcg_gen_st_i64(t8, tcg_env, vreg_ofs(s, vd) + i);
+            } else {
+                tcg_gen_ld_i64(t8, tcg_env, vreg_ofs(s, vd) + i);
+                tcg_gen_qemu_st_i64(t8, addr, s->mem_idx, MO_LEUQ | atomicity);
             }
-        } else {
-            for (int i = 0; i < size; i += 4) {
-                addr = get_address(s, rs1, i);
-                if (is_load) {
-                    tcg_gen_qemu_ld_i32(t4, addr, s->mem_idx,
-                            MO_LE | MO_32 | atomicity);
-                    tcg_gen_st_i32(t4, tcg_env, vreg_ofs(s, vd) + i);
-                } else {
-                    tcg_gen_ld_i32(t4, tcg_env, vreg_ofs(s, vd) + i);
-                    tcg_gen_qemu_st_i32(t4, addr, s->mem_idx,
-                            MO_LE | MO_32 | atomicity);
-                }
-                if (i == size - 4) {
-                    tcg_gen_movi_tl(cpu_vstart, 0);
-                } else {
-                    tcg_gen_addi_tl(cpu_vstart, cpu_vstart, 4 >> log2_esz);
-                }
+            if (i == size - 8) {
+                tcg_gen_movi_tl(cpu_vstart, 0);
+            } else {
+                tcg_gen_addi_tl(cpu_vstart, cpu_vstart, 8 >> log2_esz);
             }
         }
     } else {
-- 
2.43.0

Re: [PATCH 33/50] target/riscv: Drop TCG_TARGET_REG_BITS test

Posted by Pierrick Bouvier 1 day, 13 hours ago

On 1/7/26 9:30 PM, Richard Henderson wrote:
> Signed-off-by: Richard Henderson <richard.henderson@linaro.org>
> ---
>   target/riscv/insn_trans/trans_rvv.c.inc | 54 ++++++-------------------
>   1 file changed, 13 insertions(+), 41 deletions(-)
> 

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>