[PATCH 02/16] target/riscv: tt-ascalon: Add Svadu extension

Joel Stanley posted 16 patches 1 month ago
There is a newer version of this series
[PATCH 02/16] target/riscv: tt-ascalon: Add Svadu extension
Posted by Joel Stanley 1 month ago
From: Nicholas Piggin <npiggin@gmail.com>

Ascalon supports Svadu (hardware A/D bit updates).

QEMU makes Svadu and Svade mutually exclusive, remove Svadu so
Ascalon comes up with Svadu working.

Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
Signed-off-by: Joel Stanley <joel@jms.id.au>
---
 target/riscv/cpu.c | 1 -
 1 file changed, 1 deletion(-)

diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 2f31e79ae6cb..01bd522f9189 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -3183,7 +3183,6 @@ static const TypeInfo riscv_cpu_type_infos[] = {
         .cfg.ext_ssaia = true,
         .cfg.ext_sscofpmf = true,
         .cfg.ext_sstc = true,
-        .cfg.ext_svade = true,
         .cfg.ext_svinval = true,
         .cfg.ext_svnapot = true,
         .cfg.ext_svpbmt = true,
-- 
2.47.3