Introducing Tenstorrent Atlantis!

 The Tenstorrent Atlantis platform is a collaboration between Tenstorrent
 and CoreLab Technology. It is based on the Atlantis SoC, which includes
 the Ascalon-X CPU and other IP from Tenstorrent and CoreLab Technology.

 The Tenstorrent Ascalon-X is a high performance 64-bit RVA23 compliant
 RISC-V CPU.

This initial series adds the base machine support including:

 - AIA (Advanced Interrupt Architecture) support
 - PCIe controller and DesignWare I2C integration
 - Serial console and device tree generation
 - Functional tests for OpenSBI+Linux boot

Changes outside of adding the machine:

 - Atlantis maps DRAM high in the address space but maintains an alias
   for the first 2GB at 0x0. We have updated the RISC-V boot loader code
   to support boot_info for discontiguous memory layouts.

 - The riscv64 virt machine AIA initialisation has been moved to a
   helper file to allow code reuse with the Atlantis machine

 - Revived the DesignWare I2C controller model (previously proposed for
   ARM virt) with permission from the original author.

I hope to get early feedback on the base machine now. We intend to
continue modelling the soc so it can be useful for firmware and
operating system development and testing, so expect more patches to do
that soon.

Chris Rauer (1):
  hw/i2c: Add designware i2c controller

Joel Stanley (6):
  target/riscv: tt-ascalon: Add Tenstorrent mvendorid
  hw/riscv: Move AIA initialisation to helper file
  hw/riscv/aia: Provide number of irq sources
  hw/riscv: Add Tenstorrent Atlantis machine
  hw/riscv/atlantis: Integrate i2c buses
  hw/riscv/atlantis: Add some i2c peripherals

Nicholas Piggin (9):
  target/riscv: tt-ascalon: Enable Zkr extension
  target/riscv: tt-ascalon: Add Svadu extension
  riscv/boot: Describe discontiguous memory in boot_info
  riscv/boot: Account for discontiguous memory when loading firmware
  hw/riscv/atlantis: Add PCIe controller
  tests/functional/riscv64: Add tt-atlantis tests
  hw/riscv/boot: Warn if a ELF format file is loaded as a binary
  hw/riscv/boot: Provide a simple halting payload
  hw/riscv/atlantis: Use halting kernel if there is no payload

 MAINTAINERS                                  |  15 +
 docs/system/riscv/tt_atlantis.rst            |  38 +
 docs/system/target-riscv.rst                 |   1 +
 hw/riscv/aia.h                               |  59 ++
 include/hw/i2c/designware_i2c.h              | 101 ++
 include/hw/riscv/boot.h                      |  14 +-
 include/hw/riscv/tt_atlantis.h               |  95 ++
 include/hw/riscv/virt.h                      |  30 +-
 target/riscv/cpu_vendorid.h                  |   2 +
 hw/i2c/designware_i2c.c                      | 813 ++++++++++++++++
 hw/riscv/aia.c                               |  89 ++
 hw/riscv/boot.c                              |  73 +-
 hw/riscv/microchip_pfsoc.c                   |   6 +-
 hw/riscv/opentitan.c                         |   6 +-
 hw/riscv/shakti_c.c                          |   6 +-
 hw/riscv/sifive_u.c                          |   3 +-
 hw/riscv/spike.c                             |   6 +-
 hw/riscv/tt_atlantis.c                       | 917 +++++++++++++++++++
 hw/riscv/virt-acpi-build.c                   |  24 +-
 hw/riscv/virt.c                              |  94 +-
 hw/riscv/xiangshan_kmh.c                     |   6 +-
 target/riscv/cpu.c                           |   4 +-
 hw/i2c/Kconfig                               |   4 +
 hw/i2c/meson.build                           |   1 +
 hw/riscv/Kconfig                             |  21 +
 hw/riscv/meson.build                         |   3 +-
 tests/functional/riscv64/meson.build         |   1 +
 tests/functional/riscv64/test_opensbi.py     |   4 +
 tests/functional/riscv64/test_tt_atlantis.py |  68 ++
 29 files changed, 2365 insertions(+), 139 deletions(-)
 create mode 100644 docs/system/riscv/tt_atlantis.rst
 create mode 100644 hw/riscv/aia.h
 create mode 100644 include/hw/i2c/designware_i2c.h
 create mode 100644 include/hw/riscv/tt_atlantis.h
 create mode 100644 hw/i2c/designware_i2c.c
 create mode 100644 hw/riscv/aia.c
 create mode 100644 hw/riscv/tt_atlantis.c
 create mode 100755 tests/functional/riscv64/test_tt_atlantis.py

-- 
2.47.3

On Tue, 6 Jan 2026 at 16:27, Joel Stanley <joel@jms.id.au> wrote:
>
> Introducing Tenstorrent Atlantis!

Note that this was based on v10.2.0 and passed CI before I sent it:

  https://gitlab.com/shenki/qemu/-/pipelines/2246526243

However master has moved along and there are now some merge conflicts.
I'll hold off sending a v2 for now, but in case anyone is trying to
test, a rebased tree is here:

  https://gitlab.com/shenki/qemu/-/tree/tt-atlantis

Cheers,

Joel

Hey!

On 1/6/26 4:35 AM, Joel Stanley wrote:
> On Tue, 6 Jan 2026 at 16:27, Joel Stanley <joel@jms.id.au> wrote:
>>
>> Introducing Tenstorrent Atlantis!
> 
> Note that this was based on v10.2.0 and passed CI before I sent it:
> 
>    https://gitlab.com/shenki/qemu/-/pipelines/2246526243
> 
> However master has moved along and there are now some merge conflicts.
> I'll hold off sending a v2 for now, but in case anyone is trying to
> test, a rebased tree is here:
> 
>    https://gitlab.com/shenki/qemu/-/tree/tt-atlantis

In fact the (non-documented) practice in qemu-riscv is to send patches based on the
maintainer's tree (https://github.com/alistair23/qemu.git) branch 'riscv-to-apply.next'.

The patches don't apply in that tree too btw, but it's fine to wait for code reviews
before re-sending it.


Thanks,

Daniel







> 
> Cheers,
> 
> Joel

On 1/6/26 2:56 AM, Joel Stanley wrote:
> Introducing Tenstorrent Atlantis!
> 
>   The Tenstorrent Atlantis platform is a collaboration between Tenstorrent
>   and CoreLab Technology. It is based on the Atlantis SoC, which includes
>   the Ascalon-X CPU and other IP from Tenstorrent and CoreLab Technology.
> 
>   The Tenstorrent Ascalon-X is a high performance 64-bit RVA23 compliant
>   RISC-V CPU.
> 
> This initial series adds the base machine support including:
> 
>   - AIA (Advanced Interrupt Architecture) support
>   - PCIe controller and DesignWare I2C integration
>   - Serial console and device tree generation
>   - Functional tests for OpenSBI+Linux boot
> 
> Changes outside of adding the machine:
> 
>   - Atlantis maps DRAM high in the address space but maintains an alias
>     for the first 2GB at 0x0. We have updated the RISC-V boot loader code
>     to support boot_info for discontiguous memory layouts.
> 
>   - The riscv64 virt machine AIA initialisation has been moved to a
>     helper file to allow code reuse with the Atlantis machine
> 
>   - Revived the DesignWare I2C controller model (previously proposed for
>     ARM virt) with permission from the original author.
> 
> I hope to get early feedback on the base machine now. We intend to
> continue modelling the soc so it can be useful for firmware and
> operating system development and testing, so expect more patches to do
> that soon.

Good choice on the machine name. Looking forward for what's coming next
(Poseidon, Varuna, Anuket, Leviathan ...)

As for the patches I see stuff that could be sent separately in a prep series,
mostly the 4 patches on hw/boot and the 2 hw/aia patches. You can refer to this
prep series as a prerequisite for the main series that would include just the
machine specific stuff.

This prep series would be easier to review and would probably be merged first,
alleviating the review effort in the Atlantis series.

Also, the designware i2c controller patch seems fully reviewed. I advise sending
it standalone to be merged right away. I believe Alistair wouldn't mind pushing
it via qemu-riscv.


Thanks,

Daniel

> 
> Chris Rauer (1):
>    hw/i2c: Add designware i2c controller
> 
> Joel Stanley (6):
>    target/riscv: tt-ascalon: Add Tenstorrent mvendorid
>    hw/riscv: Move AIA initialisation to helper file
>    hw/riscv/aia: Provide number of irq sources
>    hw/riscv: Add Tenstorrent Atlantis machine
>    hw/riscv/atlantis: Integrate i2c buses
>    hw/riscv/atlantis: Add some i2c peripherals
> 
> Nicholas Piggin (9):
>    target/riscv: tt-ascalon: Enable Zkr extension
>    target/riscv: tt-ascalon: Add Svadu extension
>    riscv/boot: Describe discontiguous memory in boot_info
>    riscv/boot: Account for discontiguous memory when loading firmware
>    hw/riscv/atlantis: Add PCIe controller
>    tests/functional/riscv64: Add tt-atlantis tests
>    hw/riscv/boot: Warn if a ELF format file is loaded as a binary
>    hw/riscv/boot: Provide a simple halting payload
>    hw/riscv/atlantis: Use halting kernel if there is no payload
> 
>   MAINTAINERS                                  |  15 +
>   docs/system/riscv/tt_atlantis.rst            |  38 +
>   docs/system/target-riscv.rst                 |   1 +
>   hw/riscv/aia.h                               |  59 ++
>   include/hw/i2c/designware_i2c.h              | 101 ++
>   include/hw/riscv/boot.h                      |  14 +-
>   include/hw/riscv/tt_atlantis.h               |  95 ++
>   include/hw/riscv/virt.h                      |  30 +-
>   target/riscv/cpu_vendorid.h                  |   2 +
>   hw/i2c/designware_i2c.c                      | 813 ++++++++++++++++
>   hw/riscv/aia.c                               |  89 ++
>   hw/riscv/boot.c                              |  73 +-
>   hw/riscv/microchip_pfsoc.c                   |   6 +-
>   hw/riscv/opentitan.c                         |   6 +-
>   hw/riscv/shakti_c.c                          |   6 +-
>   hw/riscv/sifive_u.c                          |   3 +-
>   hw/riscv/spike.c                             |   6 +-
>   hw/riscv/tt_atlantis.c                       | 917 +++++++++++++++++++
>   hw/riscv/virt-acpi-build.c                   |  24 +-
>   hw/riscv/virt.c                              |  94 +-
>   hw/riscv/xiangshan_kmh.c                     |   6 +-
>   target/riscv/cpu.c                           |   4 +-
>   hw/i2c/Kconfig                               |   4 +
>   hw/i2c/meson.build                           |   1 +
>   hw/riscv/Kconfig                             |  21 +
>   hw/riscv/meson.build                         |   3 +-
>   tests/functional/riscv64/meson.build         |   1 +
>   tests/functional/riscv64/test_opensbi.py     |   4 +
>   tests/functional/riscv64/test_tt_atlantis.py |  68 ++
>   29 files changed, 2365 insertions(+), 139 deletions(-)
>   create mode 100644 docs/system/riscv/tt_atlantis.rst
>   create mode 100644 hw/riscv/aia.h
>   create mode 100644 include/hw/i2c/designware_i2c.h
>   create mode 100644 include/hw/riscv/tt_atlantis.h
>   create mode 100644 hw/i2c/designware_i2c.c
>   create mode 100644 hw/riscv/aia.c
>   create mode 100644 hw/riscv/tt_atlantis.c
>   create mode 100755 tests/functional/riscv64/test_tt_atlantis.py
>

On Wed, 7 Jan 2026 at 23:51, Daniel Henrique Barboza
<dbarboza@ventanamicro.com> wrote:
>
>
>
> On 1/6/26 2:56 AM, Joel Stanley wrote:

> > I hope to get early feedback on the base machine now. We intend to
> > continue modelling the soc so it can be useful for firmware and
> > operating system development and testing, so expect more patches to do
> > that soon.
>
> Good choice on the machine name. Looking forward for what's coming next
> (Poseidon, Varuna, Anuket, Leviathan ...)
>
> As for the patches I see stuff that could be sent separately in a prep series,
> mostly the 4 patches on hw/boot and the 2 hw/aia patches. You can refer to this
> prep series as a prerequisite for the main series that would include just the
> machine specific stuff.
>
> This prep series would be easier to review and would probably be merged first,
> alleviating the review effort in the Atlantis series.

Good plan. I'll send a series of prep patches out, based on riscv-to-apply.next.

> Also, the designware i2c controller patch seems fully reviewed. I advise sending
> it standalone to be merged right away. I believe Alistair wouldn't mind pushing
> it via qemu-riscv.

Okay, I'll do that too. Thanks for the advice.

Cheers,

Joel