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[PATCH v15 00/12] riscv: Add support for MIPS P8700 CPU

Djordje Todorovic posted 12 patches 1 month, 2 weeks ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20251223094739.1983381-1-djordje.todorovic@htecgroup.com
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Paolo Bonzini <pbonzini@redhat.com>
There is a newer version of this series
configs/devices/riscv64-softmmu/default.mak |   1 +
docs/system/riscv/mips.rst                  |  20 +
docs/system/target-riscv.rst                |   1 +
hw/misc/Kconfig                             |  17 +
hw/misc/meson.build                         |   3 +
hw/misc/riscv_cmgcr.c                       | 243 ++++++++++
hw/misc/riscv_cpc.c                         | 265 +++++++++++
hw/riscv/Kconfig                            |   6 +
hw/riscv/boston-aia.c                       | 476 ++++++++++++++++++++
hw/riscv/cps.c                              | 196 ++++++++
hw/riscv/meson.build                        |   3 +
include/hw/misc/riscv_cmgcr.h               |  48 ++
include/hw/misc/riscv_cpc.h                 |  64 +++
include/hw/riscv/cps.h                      |  66 +++
target/riscv/cpu-qom.h                      |   1 +
target/riscv/cpu.c                          |  44 ++
target/riscv/cpu.h                          |   7 +
target/riscv/cpu_cfg.h                      |   5 +
target/riscv/cpu_cfg_fields.h.inc           |   3 +
target/riscv/cpu_vendorid.h                 |   1 +
target/riscv/insn_trans/trans_xmips.c.inc   | 136 ++++++
target/riscv/meson.build                    |   2 +
target/riscv/mips_csr.c                     | 217 +++++++++
target/riscv/translate.c                    |   3 +
target/riscv/xmips.decode                   |  35 ++
tests/functional/riscv64/meson.build        |   2 +
tests/functional/riscv64/test_boston.py     | 123 +++++
27 files changed, 1988 insertions(+)
create mode 100644 docs/system/riscv/mips.rst
create mode 100644 hw/misc/riscv_cmgcr.c
create mode 100644 hw/misc/riscv_cpc.c
create mode 100644 hw/riscv/boston-aia.c
create mode 100644 hw/riscv/cps.c
create mode 100644 include/hw/misc/riscv_cmgcr.h
create mode 100644 include/hw/misc/riscv_cpc.h
create mode 100644 include/hw/riscv/cps.h
create mode 100644 target/riscv/insn_trans/trans_xmips.c.inc
create mode 100644 target/riscv/mips_csr.c
create mode 100644 target/riscv/xmips.decode
create mode 100755 tests/functional/riscv64/test_boston.py
[PATCH v15 00/12] riscv: Add support for MIPS P8700 CPU
Posted by Djordje Todorovic 1 month, 2 weeks ago 
Rebased on top of master branch and removed patches that are merged.

Djordje Todorovic (12):
  target/riscv: Add cpu_set_exception_base
  target/riscv: Add MIPS P8700 CPU
  target/riscv: Add MIPS P8700 CSRs
  target/riscv: Add mips.ccmov instruction
  target/riscv: Add mips.pref instruction
  target/riscv: Add Xmipslsp instructions
  hw/misc: Add RISC-V CMGCR device implementation
  hw/misc: Add RISC-V CPC device implementation
  hw/riscv: Add support for RISCV CPS
  hw/riscv: Add support for MIPS Boston-aia board mode
  riscv/boston-aia: Add an e1000e NIC in slot 0 func 1
  test/functional: Add test for boston-aia board

 configs/devices/riscv64-softmmu/default.mak |   1 +
 docs/system/riscv/mips.rst                  |  20 +
 docs/system/target-riscv.rst                |   1 +
 hw/misc/Kconfig                             |  17 +
 hw/misc/meson.build                         |   3 +
 hw/misc/riscv_cmgcr.c                       | 243 ++++++++++
 hw/misc/riscv_cpc.c                         | 265 +++++++++++
 hw/riscv/Kconfig                            |   6 +
 hw/riscv/boston-aia.c                       | 476 ++++++++++++++++++++
 hw/riscv/cps.c                              | 196 ++++++++
 hw/riscv/meson.build                        |   3 +
 include/hw/misc/riscv_cmgcr.h               |  48 ++
 include/hw/misc/riscv_cpc.h                 |  64 +++
 include/hw/riscv/cps.h                      |  66 +++
 target/riscv/cpu-qom.h                      |   1 +
 target/riscv/cpu.c                          |  44 ++
 target/riscv/cpu.h                          |   7 +
 target/riscv/cpu_cfg.h                      |   5 +
 target/riscv/cpu_cfg_fields.h.inc           |   3 +
 target/riscv/cpu_vendorid.h                 |   1 +
 target/riscv/insn_trans/trans_xmips.c.inc   | 136 ++++++
 target/riscv/meson.build                    |   2 +
 target/riscv/mips_csr.c                     | 217 +++++++++
 target/riscv/translate.c                    |   3 +
 target/riscv/xmips.decode                   |  35 ++
 tests/functional/riscv64/meson.build        |   2 +
 tests/functional/riscv64/test_boston.py     | 123 +++++
 27 files changed, 1988 insertions(+)
 create mode 100644 docs/system/riscv/mips.rst
 create mode 100644 hw/misc/riscv_cmgcr.c
 create mode 100644 hw/misc/riscv_cpc.c
 create mode 100644 hw/riscv/boston-aia.c
 create mode 100644 hw/riscv/cps.c
 create mode 100644 include/hw/misc/riscv_cmgcr.h
 create mode 100644 include/hw/misc/riscv_cpc.h
 create mode 100644 include/hw/riscv/cps.h
 create mode 100644 target/riscv/insn_trans/trans_xmips.c.inc
 create mode 100644 target/riscv/mips_csr.c
 create mode 100644 target/riscv/xmips.decode
 create mode 100755 tests/functional/riscv64/test_boston.py

-- 
2.34.1
Re: [PATCH v15 00/12] riscv: Add support for MIPS P8700 CPU
Posted by Alistair Francis 1 month ago 
On Tue, Dec 23, 2025 at 7:47 PM Djordje Todorovic
<Djordje.Todorovic@htecgroup.com> wrote:
>
> Rebased on top of master branch and removed patches that are merged.
>
> Djordje Todorovic (12):
>   target/riscv: Add cpu_set_exception_base
>   target/riscv: Add MIPS P8700 CPU
>   target/riscv: Add MIPS P8700 CSRs
>   target/riscv: Add mips.ccmov instruction
>   target/riscv: Add mips.pref instruction
>   target/riscv: Add Xmipslsp instructions
>   hw/misc: Add RISC-V CMGCR device implementation
>   hw/misc: Add RISC-V CPC device implementation
>   hw/riscv: Add support for RISCV CPS
>   hw/riscv: Add support for MIPS Boston-aia board mode
>   riscv/boston-aia: Add an e1000e NIC in slot 0 func 1
>   test/functional: Add test for boston-aia board
>
>  configs/devices/riscv64-softmmu/default.mak |   1 +
>  docs/system/riscv/mips.rst                  |  20 +
>  docs/system/target-riscv.rst                |   1 +
>  hw/misc/Kconfig                             |  17 +
>  hw/misc/meson.build                         |   3 +
>  hw/misc/riscv_cmgcr.c                       | 243 ++++++++++
>  hw/misc/riscv_cpc.c                         | 265 +++++++++++
>  hw/riscv/Kconfig                            |   6 +
>  hw/riscv/boston-aia.c                       | 476 ++++++++++++++++++++
>  hw/riscv/cps.c                              | 196 ++++++++
>  hw/riscv/meson.build                        |   3 +
>  include/hw/misc/riscv_cmgcr.h               |  48 ++
>  include/hw/misc/riscv_cpc.h                 |  64 +++
>  include/hw/riscv/cps.h                      |  66 +++
>  target/riscv/cpu-qom.h                      |   1 +
>  target/riscv/cpu.c                          |  44 ++
>  target/riscv/cpu.h                          |   7 +
>  target/riscv/cpu_cfg.h                      |   5 +
>  target/riscv/cpu_cfg_fields.h.inc           |   3 +
>  target/riscv/cpu_vendorid.h                 |   1 +
>  target/riscv/insn_trans/trans_xmips.c.inc   | 136 ++++++
>  target/riscv/meson.build                    |   2 +
>  target/riscv/mips_csr.c                     | 217 +++++++++
>  target/riscv/translate.c                    |   3 +
>  target/riscv/xmips.decode                   |  35 ++
>  tests/functional/riscv64/meson.build        |   2 +
>  tests/functional/riscv64/test_boston.py     | 123 +++++
>  27 files changed, 1988 insertions(+)
>  create mode 100644 docs/system/riscv/mips.rst
>  create mode 100644 hw/misc/riscv_cmgcr.c
>  create mode 100644 hw/misc/riscv_cpc.c
>  create mode 100644 hw/riscv/boston-aia.c
>  create mode 100644 hw/riscv/cps.c
>  create mode 100644 include/hw/misc/riscv_cmgcr.h
>  create mode 100644 include/hw/misc/riscv_cpc.h
>  create mode 100644 include/hw/riscv/cps.h
>  create mode 100644 target/riscv/insn_trans/trans_xmips.c.inc
>  create mode 100644 target/riscv/mips_csr.c
>  create mode 100644 target/riscv/xmips.decode
>  create mode 100755 tests/functional/riscv64/test_boston.py

This has a few build errors, things like

../hw/misc/riscv_cmgcr.c:18:10: fatal error: hw/sysbus.h: No such file
or directory
  18 | #include "hw/sysbus.h"
     |          ^~~~~~~~~~~~~
compilation terminated.
[528/1079] Compiling C object li

I tried fixing those for you, but there are other build errors that
need to be fixed.

Alistair

>
> --
> 2.34.1
Re: [PATCH v15 00/12] riscv: Add support for MIPS P8700 CPU
Posted by Djordje Todorovic 1 month ago 
Public

Hi Alistair,

>I tried fixing those for you, but there are other build errors that
>need to be fixed.

I see. It is due to the latest movement of these files into hw/core/.
I will rebase again and address it.

Best,
Djordje

________________________________
From: Alistair Francis <alistair23@gmail.com>
Sent: Monday, January 5, 2026 3:35 AM
To: Djordje Todorovic <Djordje.Todorovic@htecgroup.com>
Cc: qemu-devel@nongnu.org <qemu-devel@nongnu.org>; qemu-riscv@nongnu.org <qemu-riscv@nongnu.org>; cfu@mips.com <cfu@mips.com>; mst@redhat.com <mst@redhat.com>; marcel.apfelbaum@gmail.com <marcel.apfelbaum@gmail.com>; dbarboza@ventanamicro.com <dbarboza@ventanamicro.com>; philmd@linaro.org <philmd@linaro.org>; thuth@redhat.com <thuth@redhat.com>
Subject: Re: [PATCH v15 00/12] riscv: Add support for MIPS P8700 CPU

CAUTION: This email originated from outside of the organization. Do not click links or open attachments unless you recognize the sender and know the content is safe.


On Tue, Dec 23, 2025 at 7:47 PM Djordje Todorovic
<Djordje.Todorovic@htecgroup.com> wrote:
>
> Rebased on top of master branch and removed patches that are merged.
>
> Djordje Todorovic (12):
>   target/riscv: Add cpu_set_exception_base
>   target/riscv: Add MIPS P8700 CPU
>   target/riscv: Add MIPS P8700 CSRs
>   target/riscv: Add mips.ccmov instruction
>   target/riscv: Add mips.pref instruction
>   target/riscv: Add Xmipslsp instructions
>   hw/misc: Add RISC-V CMGCR device implementation
>   hw/misc: Add RISC-V CPC device implementation
>   hw/riscv: Add support for RISCV CPS
>   hw/riscv: Add support for MIPS Boston-aia board mode
>   riscv/boston-aia: Add an e1000e NIC in slot 0 func 1
>   test/functional: Add test for boston-aia board
>
>  configs/devices/riscv64-softmmu/default.mak |   1 +
>  docs/system/riscv/mips.rst                  |  20 +
>  docs/system/target-riscv.rst                |   1 +
>  hw/misc/Kconfig                             |  17 +
>  hw/misc/meson.build                         |   3 +
>  hw/misc/riscv_cmgcr.c                       | 243 ++++++++++
>  hw/misc/riscv_cpc.c                         | 265 +++++++++++
>  hw/riscv/Kconfig                            |   6 +
>  hw/riscv/boston-aia.c                       | 476 ++++++++++++++++++++
>  hw/riscv/cps.c                              | 196 ++++++++
>  hw/riscv/meson.build                        |   3 +
>  include/hw/misc/riscv_cmgcr.h               |  48 ++
>  include/hw/misc/riscv_cpc.h                 |  64 +++
>  include/hw/riscv/cps.h                      |  66 +++
>  target/riscv/cpu-qom.h                      |   1 +
>  target/riscv/cpu.c                          |  44 ++
>  target/riscv/cpu.h                          |   7 +
>  target/riscv/cpu_cfg.h                      |   5 +
>  target/riscv/cpu_cfg_fields.h.inc           |   3 +
>  target/riscv/cpu_vendorid.h                 |   1 +
>  target/riscv/insn_trans/trans_xmips.c.inc   | 136 ++++++
>  target/riscv/meson.build                    |   2 +
>  target/riscv/mips_csr.c                     | 217 +++++++++
>  target/riscv/translate.c                    |   3 +
>  target/riscv/xmips.decode                   |  35 ++
>  tests/functional/riscv64/meson.build        |   2 +
>  tests/functional/riscv64/test_boston.py     | 123 +++++
>  27 files changed, 1988 insertions(+)
>  create mode 100644 docs/system/riscv/mips.rst
>  create mode 100644 hw/misc/riscv_cmgcr.c
>  create mode 100644 hw/misc/riscv_cpc.c
>  create mode 100644 hw/riscv/boston-aia.c
>  create mode 100644 hw/riscv/cps.c
>  create mode 100644 include/hw/misc/riscv_cmgcr.h
>  create mode 100644 include/hw/misc/riscv_cpc.h
>  create mode 100644 include/hw/riscv/cps.h
>  create mode 100644 target/riscv/insn_trans/trans_xmips.c.inc
>  create mode 100644 target/riscv/mips_csr.c
>  create mode 100644 target/riscv/xmips.decode
>  create mode 100755 tests/functional/riscv64/test_boston.py

This has a few build errors, things like

../hw/misc/riscv_cmgcr.c:18:10: fatal error: hw/sysbus.h: No such file
or directory
  18 | #include "hw/sysbus.h"
     |          ^~~~~~~~~~~~~
compilation terminated.
[528/1079] Compiling C object li

I tried fixing those for you, but there are other build errors that
need to be fixed.

Alistair

>
> --
> 2.34.1

Patchew 2.1-devel-b67e4c2

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