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[PATCH] target/hexagon: Widen MemLog::width to 32 bits

Anton Johansson via posted 1 patch 1 month, 2 weeks ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20251221142232.22738-1-anjo@rev.ng
Maintainers: Brian Cain <brian.cain@oss.qualcomm.com>
There is a newer version of this series
target/hexagon/cpu.h       | 2 +-
target/hexagon/op_helper.h | 4 ++--
target/hexagon/translate.h | 2 +-
target/hexagon/genptr.c    | 6 +++---
target/hexagon/op_helper.c | 4 ++--
target/hexagon/translate.c | 4 ++--
6 files changed, 11 insertions(+), 11 deletions(-)
[PATCH] target/hexagon: Widen MemLog::width to 32 bits
Posted by Anton Johansson via 1 month, 2 weeks ago 
MemLog::width is a uint8_t value mapped to a TCGv (32 bit), the only
reason this currently works is because MemLog::width is padded to 32
bits.  Widen the field to uint32_t and fix the size of the TCGv
operations as well.  Use uint8_t when passing around the
field as an immediate to retain previous truncation behaviour.

Signed-off-by: Anton Johansson <anjo@rev.ng>
---
 target/hexagon/cpu.h       | 2 +-
 target/hexagon/op_helper.h | 4 ++--
 target/hexagon/translate.h | 2 +-
 target/hexagon/genptr.c    | 6 +++---
 target/hexagon/op_helper.c | 4 ++--
 target/hexagon/translate.c | 4 ++--
 6 files changed, 11 insertions(+), 11 deletions(-)

diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
index 43a854f517..9d3df84ee6 100644
--- a/target/hexagon/cpu.h
+++ b/target/hexagon/cpu.h
@@ -46,7 +46,7 @@
 
 typedef struct {
     target_ulong va;
-    uint8_t width;
+    uint32_t width;
     uint32_t data32;
     uint64_t data64;
 } MemLog;
diff --git a/target/hexagon/op_helper.h b/target/hexagon/op_helper.h
index 66119cf3d4..ff65a94d57 100644
--- a/target/hexagon/op_helper.h
+++ b/target/hexagon/op_helper.h
@@ -20,8 +20,8 @@
 
 /* Misc functions */
 void log_store64(CPUHexagonState *env, target_ulong addr,
-                 int64_t val, int width, int slot);
+                 int64_t val, uint8_t width, int slot);
 void log_store32(CPUHexagonState *env, target_ulong addr,
-                 target_ulong val, int width, int slot);
+                 target_ulong val, uint8_t width, int slot);
 
 #endif
diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
index d251e2233f..9e8f54edb5 100644
--- a/target/hexagon/translate.h
+++ b/target/hexagon/translate.h
@@ -271,7 +271,7 @@ extern TCGv hex_pred[NUM_PREGS];
 extern TCGv hex_slot_cancelled;
 extern TCGv hex_new_value_usr;
 extern TCGv hex_store_addr[STORES_MAX];
-extern TCGv hex_store_width[STORES_MAX];
+extern TCGv_i32 hex_store_width[STORES_MAX];
 extern TCGv hex_store_val32[STORES_MAX];
 extern TCGv_i64 hex_store_val64[STORES_MAX];
 extern TCGv hex_llsc_addr;
diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
index cecaece4ae..9c66ca181a 100644
--- a/target/hexagon/genptr.c
+++ b/target/hexagon/genptr.c
@@ -401,10 +401,10 @@ static TCGv gen_slotval(DisasContext *ctx)
 }
 #endif
 
-void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot)
+void gen_store32(TCGv vaddr, TCGv src, uint8_t width, uint32_t slot)
 {
     tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
-    tcg_gen_movi_tl(hex_store_width[slot], width);
+    tcg_gen_movi_i32(hex_store_width[slot], width);
     tcg_gen_mov_tl(hex_store_val32[slot], src);
 }
 
@@ -444,7 +444,7 @@ void gen_store4i(TCGv_env tcg_env, TCGv vaddr, int32_t src, uint32_t slot)
 void gen_store8(TCGv_env tcg_env, TCGv vaddr, TCGv_i64 src, uint32_t slot)
 {
     tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
-    tcg_gen_movi_tl(hex_store_width[slot], 8);
+    tcg_gen_movi_i32(hex_store_width[slot], 8);
     tcg_gen_mov_i64(hex_store_val64[slot], src);
 }
 
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index e2e80ca7ef..823307696d 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -52,7 +52,7 @@ G_NORETURN void HELPER(raise_exception)(CPUHexagonState *env, uint32_t excp)
 }
 
 void log_store32(CPUHexagonState *env, target_ulong addr,
-                 target_ulong val, int width, int slot)
+                 target_ulong val, uint8_t width, int slot)
 {
     env->mem_log_stores[slot].va = addr;
     env->mem_log_stores[slot].width = width;
@@ -60,7 +60,7 @@ void log_store32(CPUHexagonState *env, target_ulong addr,
 }
 
 void log_store64(CPUHexagonState *env, target_ulong addr,
-                 int64_t val, int width, int slot)
+                 int64_t val, uint8_t width, int slot)
 {
     env->mem_log_stores[slot].va = addr;
     env->mem_log_stores[slot].width = width;
diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
index 8fce219c0d..6151bdd4a6 100644
--- a/target/hexagon/translate.c
+++ b/target/hexagon/translate.c
@@ -51,7 +51,7 @@ TCGv hex_pred[NUM_PREGS];
 TCGv hex_slot_cancelled;
 TCGv hex_new_value_usr;
 TCGv hex_store_addr[STORES_MAX];
-TCGv hex_store_width[STORES_MAX];
+TCGv_i32 hex_store_width[STORES_MAX];
 TCGv hex_store_val32[STORES_MAX];
 TCGv_i64 hex_store_val64[STORES_MAX];
 TCGv hex_llsc_addr;
@@ -1079,7 +1079,7 @@ void hexagon_translate_init(void)
             store_addr_names[i]);
 
         snprintf(store_width_names[i], NAME_LEN, "store_width_%d", i);
-        hex_store_width[i] = tcg_global_mem_new(tcg_env,
+        hex_store_width[i] = tcg_global_mem_new_i32(tcg_env,
             offsetof(CPUHexagonState, mem_log_stores[i].width),
             store_width_names[i]);
 
-- 
2.51.0
Re: [PATCH] target/hexagon: Widen MemLog::width to 32 bits
Posted by Philippe Mathieu-Daudé 1 month ago 
On 21/12/25 15:22, Anton Johansson via wrote:
> MemLog::width is a uint8_t value mapped to a TCGv (32 bit), the only
> reason this currently works is because MemLog::width is padded to 32
> bits.  Widen the field to uint32_t and fix the size of the TCGv
> operations as well.  Use uint8_t when passing around the
> field as an immediate to retain previous truncation behaviour.
> 
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
>   target/hexagon/cpu.h       | 2 +-
>   target/hexagon/op_helper.h | 4 ++--
>   target/hexagon/translate.h | 2 +-
>   target/hexagon/genptr.c    | 6 +++---
>   target/hexagon/op_helper.c | 4 ++--
>   target/hexagon/translate.c | 4 ++--
>   6 files changed, 11 insertions(+), 11 deletions(-)


> diff --git a/target/hexagon/op_helper.h b/target/hexagon/op_helper.h
> index 66119cf3d4..ff65a94d57 100644
> --- a/target/hexagon/op_helper.h
> +++ b/target/hexagon/op_helper.h
> @@ -20,8 +20,8 @@
>   
>   /* Misc functions */
>   void log_store64(CPUHexagonState *env, target_ulong addr,
> -                 int64_t val, int width, int slot);
> +                 int64_t val, uint8_t width, int slot);
>   void log_store32(CPUHexagonState *env, target_ulong addr,
> -                 target_ulong val, int width, int slot);
> +                 target_ulong val, uint8_t width, int slot);

With the rationale of this commit, I'm not really keen on using
a uint8_t to truncate. Can we use a uint32_t but assert for a
valid range, or do an explicit truncation?
Re: [PATCH] target/hexagon: Widen MemLog::width to 32 bits
Posted by Brian Cain 1 month ago 
On Sun, Dec 21, 2025 at 8:19 AM Anton Johansson <anjo@rev.ng> wrote:

> MemLog::width is a uint8_t value mapped to a TCGv (32 bit), the only
> reason this currently works is because MemLog::width is padded to 32
> bits.  Widen the field to uint32_t and fix the size of the TCGv
> operations as well.  Use uint8_t when passing around the
> field as an immediate to retain previous truncation behaviour.
>
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
>

Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>

 target/hexagon/cpu.h       | 2 +-
>  target/hexagon/op_helper.h | 4 ++--
>  target/hexagon/translate.h | 2 +-
>  target/hexagon/genptr.c    | 6 +++---
>  target/hexagon/op_helper.c | 4 ++--
>  target/hexagon/translate.c | 4 ++--
>  6 files changed, 11 insertions(+), 11 deletions(-)
>
> diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h
> index 43a854f517..9d3df84ee6 100644
> --- a/target/hexagon/cpu.h
> +++ b/target/hexagon/cpu.h
> @@ -46,7 +46,7 @@
>
>  typedef struct {
>      target_ulong va;
> -    uint8_t width;
> +    uint32_t width;
>      uint32_t data32;
>      uint64_t data64;
>  } MemLog;
> diff --git a/target/hexagon/op_helper.h b/target/hexagon/op_helper.h
> index 66119cf3d4..ff65a94d57 100644
> --- a/target/hexagon/op_helper.h
> +++ b/target/hexagon/op_helper.h
> @@ -20,8 +20,8 @@
>
>  /* Misc functions */
>  void log_store64(CPUHexagonState *env, target_ulong addr,
> -                 int64_t val, int width, int slot);
> +                 int64_t val, uint8_t width, int slot);
>  void log_store32(CPUHexagonState *env, target_ulong addr,
> -                 target_ulong val, int width, int slot);
> +                 target_ulong val, uint8_t width, int slot);
>
>  #endif
> diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h
> index d251e2233f..9e8f54edb5 100644
> --- a/target/hexagon/translate.h
> +++ b/target/hexagon/translate.h
> @@ -271,7 +271,7 @@ extern TCGv hex_pred[NUM_PREGS];
>  extern TCGv hex_slot_cancelled;
>  extern TCGv hex_new_value_usr;
>  extern TCGv hex_store_addr[STORES_MAX];
> -extern TCGv hex_store_width[STORES_MAX];
> +extern TCGv_i32 hex_store_width[STORES_MAX];
>  extern TCGv hex_store_val32[STORES_MAX];
>  extern TCGv_i64 hex_store_val64[STORES_MAX];
>  extern TCGv hex_llsc_addr;
> diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c
> index cecaece4ae..9c66ca181a 100644
> --- a/target/hexagon/genptr.c
> +++ b/target/hexagon/genptr.c
> @@ -401,10 +401,10 @@ static TCGv gen_slotval(DisasContext *ctx)
>  }
>  #endif
>
> -void gen_store32(TCGv vaddr, TCGv src, int width, uint32_t slot)
> +void gen_store32(TCGv vaddr, TCGv src, uint8_t width, uint32_t slot)
>  {
>      tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
> -    tcg_gen_movi_tl(hex_store_width[slot], width);
> +    tcg_gen_movi_i32(hex_store_width[slot], width);
>      tcg_gen_mov_tl(hex_store_val32[slot], src);
>  }
>
> @@ -444,7 +444,7 @@ void gen_store4i(TCGv_env tcg_env, TCGv vaddr, int32_t
> src, uint32_t slot)
>  void gen_store8(TCGv_env tcg_env, TCGv vaddr, TCGv_i64 src, uint32_t slot)
>  {
>      tcg_gen_mov_tl(hex_store_addr[slot], vaddr);
> -    tcg_gen_movi_tl(hex_store_width[slot], 8);
> +    tcg_gen_movi_i32(hex_store_width[slot], 8);
>      tcg_gen_mov_i64(hex_store_val64[slot], src);
>  }
>
> diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
> index e2e80ca7ef..823307696d 100644
> --- a/target/hexagon/op_helper.c
> +++ b/target/hexagon/op_helper.c
> @@ -52,7 +52,7 @@ G_NORETURN void HELPER(raise_exception)(CPUHexagonState
> *env, uint32_t excp)
>  }
>
>  void log_store32(CPUHexagonState *env, target_ulong addr,
> -                 target_ulong val, int width, int slot)
> +                 target_ulong val, uint8_t width, int slot)
>  {
>      env->mem_log_stores[slot].va = addr;
>      env->mem_log_stores[slot].width = width;
> @@ -60,7 +60,7 @@ void log_store32(CPUHexagonState *env, target_ulong addr,
>  }
>
>  void log_store64(CPUHexagonState *env, target_ulong addr,
> -                 int64_t val, int width, int slot)
> +                 int64_t val, uint8_t width, int slot)
>  {
>      env->mem_log_stores[slot].va = addr;
>      env->mem_log_stores[slot].width = width;
> diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c
> index 8fce219c0d..6151bdd4a6 100644
> --- a/target/hexagon/translate.c
> +++ b/target/hexagon/translate.c
> @@ -51,7 +51,7 @@ TCGv hex_pred[NUM_PREGS];
>  TCGv hex_slot_cancelled;
>  TCGv hex_new_value_usr;
>  TCGv hex_store_addr[STORES_MAX];
> -TCGv hex_store_width[STORES_MAX];
> +TCGv_i32 hex_store_width[STORES_MAX];
>  TCGv hex_store_val32[STORES_MAX];
>  TCGv_i64 hex_store_val64[STORES_MAX];
>  TCGv hex_llsc_addr;
> @@ -1079,7 +1079,7 @@ void hexagon_translate_init(void)
>              store_addr_names[i]);
>
>          snprintf(store_width_names[i], NAME_LEN, "store_width_%d", i);
> -        hex_store_width[i] = tcg_global_mem_new(tcg_env,
> +        hex_store_width[i] = tcg_global_mem_new_i32(tcg_env,
>              offsetof(CPUHexagonState, mem_log_stores[i].width),
>              store_width_names[i]);
>
> --
> 2.51.0
>
>

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