TYPE_RISCV_CPU_BASE is used only to initialize the correct default
machine for 3 machines. Replace it with a runtime check.

Signed-off-by: Anton Johansson <anjo@rev.ng>
---
 include/hw/riscv/virt.h         | 11 +++++++++++
 target/riscv/cpu.h              |  6 ------
 hw/riscv/microblaze-v-generic.c |  3 ++-
 hw/riscv/spike.c                |  3 ++-
 hw/riscv/virt.c                 |  2 +-
 5 files changed, 16 insertions(+), 9 deletions(-)

diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h
index 7b4c2c8b7d..3a17641078 100644
--- a/include/hw/riscv/virt.h
+++ b/include/hw/riscv/virt.h
@@ -19,6 +19,7 @@
 #ifndef HW_RISCV_VIRT_H
 #define HW_RISCV_VIRT_H
 
+#include "qemu/target-info.h"
 #include "hw/boards.h"
 #include "hw/riscv/riscv_hart.h"
 #include "hw/sysbus.h"
@@ -137,6 +138,16 @@ bool virt_is_iommu_sys_enabled(RISCVVirtState *s);
 void virt_acpi_setup(RISCVVirtState *vms);
 uint32_t imsic_num_bits(uint32_t count);
 
+static inline const char *virt_default_cpu_type(void)
+{
+    if (target_riscv64()) {
+        return TYPE_RISCV_CPU_BASE64;
+    } else {
+        return TYPE_RISCV_CPU_BASE32;
+    }
+}
+
+
 /*
  * The virt machine physical address space used by some of the devices
  * namely ACLINT, PLIC, APLIC, and IMSIC depend on number of Sockets,
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 616406f07f..da2bc554d3 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -39,12 +39,6 @@ typedef struct CPUArchState CPURISCVState;
 
 #define CPU_RESOLVING_TYPE TYPE_RISCV_CPU
 
-#if defined(TARGET_RISCV32)
-# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE32
-#elif defined(TARGET_RISCV64)
-# define TYPE_RISCV_CPU_BASE            TYPE_RISCV_CPU_BASE64
-#endif
-
 /*
  * b0: Whether a instruction always raise a store AMO or not.
  */
diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generic.c
index 0df276f9fb..0222ff0c06 100644
--- a/hw/riscv/microblaze-v-generic.c
+++ b/hw/riscv/microblaze-v-generic.c
@@ -26,6 +26,7 @@
 #include "hw/char/xilinx_uartlite.h"
 #include "hw/misc/unimp.h"
 #include "hw/riscv/machines-qom.h"
+#include "hw/riscv/virt.h"
 
 #define LMB_BRAM_SIZE (128 * KiB)
 #define MEMORY_BASEADDR 0x80000000
@@ -183,7 +184,7 @@ static void mb_v_generic_machine_init(MachineClass *mc)
     mc->init = mb_v_generic_init;
     mc->min_cpus = 1;
     mc->max_cpus = 1;
-    mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
+    mc->default_cpu_type = virt_default_cpu_type();
     mc->default_cpus = 1;
 }
 
diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c
index 69eb3dfc24..7d1a642a78 100644
--- a/hw/riscv/spike.c
+++ b/hw/riscv/spike.c
@@ -34,6 +34,7 @@
 #include "hw/riscv/boot.h"
 #include "hw/riscv/numa.h"
 #include "hw/riscv/machines-qom.h"
+#include "hw/riscv/virt.h"
 #include "hw/char/riscv_htif.h"
 #include "hw/intc/riscv_aclint.h"
 #include "chardev/char.h"
@@ -351,7 +352,7 @@ static void spike_machine_class_init(ObjectClass *oc, const void *data)
     mc->init = spike_board_init;
     mc->max_cpus = SPIKE_CPUS_MAX;
     mc->is_default = true;
-    mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
+    mc->default_cpu_type = virt_default_cpu_type();
     mc->possible_cpu_arch_ids = riscv_numa_possible_cpu_arch_ids;
     mc->cpu_index_to_instance_props = riscv_numa_cpu_index_to_props;
     mc->get_default_cpu_node_id = riscv_numa_get_default_cpu_node_id;
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c
index f42fffb223..6f6164e05d 100644
--- a/hw/riscv/virt.c
+++ b/hw/riscv/virt.c
@@ -1922,7 +1922,7 @@ static void virt_machine_class_init(ObjectClass *oc, const void *data)
     mc->desc = "RISC-V VirtIO board";
     mc->init = virt_machine_init;
     mc->max_cpus = VIRT_CPUS_MAX;
-    mc->default_cpu_type = TYPE_RISCV_CPU_BASE;
+    mc->default_cpu_type = virt_default_cpu_type();
     mc->block_default_type = IF_VIRTIO;
     mc->no_cdrom = 1;
     mc->pci_allow_0_address = true;

-- 
2.51.0

On 12/16/25 3:51 PM, Anton Johansson wrote:
> TYPE_RISCV_CPU_BASE is used only to initialize the correct default
> machine for 3 machines. Replace it with a runtime check.
> 
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
>   include/hw/riscv/virt.h         | 11 +++++++++++
>   target/riscv/cpu.h              |  6 ------
>   hw/riscv/microblaze-v-generic.c |  3 ++-
>   hw/riscv/spike.c                |  3 ++-
>   hw/riscv/virt.c                 |  2 +-
>   5 files changed, 16 insertions(+), 9 deletions(-)
Using directly class->default_cpu_type instead of callback 
class->get_default_cpu_type() works here compared to hw/arm/virt because 
default cpu type does not depend on accelerator used, and we already 
will know what would be the runtime target at this point.

Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>