single-binary: Compile hw/riscv once

[PATCH 13/14] hw/riscv: Define SiFive E/U CPUs using runtime conditions

Posted by Anton Johansson via 1 day, 8 hours ago

Signed-off-by: Anton Johansson <anjo@rev.ng>
---
 include/hw/riscv/sifive_cpu.h | 26 +++++++++++++++++++-------
 hw/riscv/sifive_e.c           |  2 +-
 hw/riscv/sifive_u.c           |  4 ++--
 3 files changed, 22 insertions(+), 10 deletions(-)

diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h
index 136799633a..8391141d5e 100644
--- a/include/hw/riscv/sifive_cpu.h
+++ b/include/hw/riscv/sifive_cpu.h
@@ -20,12 +20,24 @@
 #ifndef HW_SIFIVE_CPU_H
 #define HW_SIFIVE_CPU_H
 
-#if defined(TARGET_RISCV32)
-#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31
-#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34
-#elif defined(TARGET_RISCV64)
-#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
-#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
-#endif
+#include "qemu/target-info.h"
+
+static inline const char *sifive_e_cpu(void)
+{
+    if (target_riscv64()) {
+        return TYPE_RISCV_CPU_SIFIVE_E51;
+    } else {
+        return TYPE_RISCV_CPU_SIFIVE_E31;
+    }
+}
+
+static inline const char *sifive_u_cpu(void)
+{
+    if (target_riscv64()) {
+        return TYPE_RISCV_CPU_SIFIVE_U54;
+    } else {
+        return TYPE_RISCV_CPU_SIFIVE_U34;
+    }
+}
 
 #endif /* HW_SIFIVE_CPU_H */
diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
index 7ed419cf69..458b21b9e3 100644
--- a/hw/riscv/sifive_e.c
+++ b/hw/riscv/sifive_e.c
@@ -151,7 +151,7 @@ static void sifive_e_machine_class_init(ObjectClass *oc, const void *data)
     mc->desc = "RISC-V Board compatible with SiFive E SDK";
     mc->init = sifive_e_machine_init;
     mc->max_cpus = 1;
-    mc->default_cpu_type = SIFIVE_E_CPU;
+    mc->default_cpu_type = sifive_e_cpu();
     mc->default_ram_id = "riscv.sifive.e.ram";
     mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size;
 
diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
index 2ff2059bb9..a04481806e 100644
--- a/hw/riscv/sifive_u.c
+++ b/hw/riscv/sifive_u.c
@@ -723,7 +723,7 @@ static void sifive_u_machine_class_init(ObjectClass *oc, const void *data)
     mc->init = sifive_u_machine_init;
     mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
     mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
-    mc->default_cpu_type = SIFIVE_U_CPU;
+    mc->default_cpu_type = sifive_u_cpu();
     mc->default_cpus = mc->min_cpus;
     mc->default_ram_id = "riscv.sifive.u.ram";
     mc->auto_create_sdcard = true;
@@ -764,7 +764,7 @@ static void sifive_u_soc_instance_init(Object *obj)
                             TYPE_RISCV_HART_ARRAY);
     qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
     qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
-    qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
+    qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", sifive_e_cpu());
     qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
 
     object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);

-- 
2.51.0

Re: [PATCH 13/14] hw/riscv: Define SiFive E/U CPUs using runtime conditions

Posted by Philippe Mathieu-Daudé 16 hours ago

On 17/12/25 00:51, Anton Johansson wrote:
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
>   include/hw/riscv/sifive_cpu.h | 26 +++++++++++++++++++-------
>   hw/riscv/sifive_e.c           |  2 +-
>   hw/riscv/sifive_u.c           |  4 ++--
>   3 files changed, 22 insertions(+), 10 deletions(-)
> 
> diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h
> index 136799633a..8391141d5e 100644
> --- a/include/hw/riscv/sifive_cpu.h
> +++ b/include/hw/riscv/sifive_cpu.h
> @@ -20,12 +20,24 @@
>   #ifndef HW_SIFIVE_CPU_H
>   #define HW_SIFIVE_CPU_H
>   
> -#if defined(TARGET_RISCV32)
> -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31
> -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34
> -#elif defined(TARGET_RISCV64)
> -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
> -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
> -#endif
> +#include "qemu/target-info.h"
> +
> +static inline const char *sifive_e_cpu(void)
> +{
> +    if (target_riscv64()) {
> +        return TYPE_RISCV_CPU_SIFIVE_E51;
> +    } else {
> +        return TYPE_RISCV_CPU_SIFIVE_E31;
> +    }
> +}
> +
> +static inline const char *sifive_u_cpu(void)
> +{
> +    if (target_riscv64()) {
> +        return TYPE_RISCV_CPU_SIFIVE_U54;
> +    } else {
> +        return TYPE_RISCV_CPU_SIFIVE_U34;
> +    }
> +}
>   
>   #endif /* HW_SIFIVE_CPU_H */
> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
> index 7ed419cf69..458b21b9e3 100644
> --- a/hw/riscv/sifive_e.c
> +++ b/hw/riscv/sifive_e.c
> @@ -151,7 +151,7 @@ static void sifive_e_machine_class_init(ObjectClass *oc, const void *data)
>       mc->desc = "RISC-V Board compatible with SiFive E SDK";
>       mc->init = sifive_e_machine_init;
>       mc->max_cpus = 1;
> -    mc->default_cpu_type = SIFIVE_E_CPU;
> +    mc->default_cpu_type = sifive_e_cpu();
>       mc->default_ram_id = "riscv.sifive.e.ram";
>       mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size;
>   
> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
> index 2ff2059bb9..a04481806e 100644
> --- a/hw/riscv/sifive_u.c
> +++ b/hw/riscv/sifive_u.c
> @@ -723,7 +723,7 @@ static void sifive_u_machine_class_init(ObjectClass *oc, const void *data)
>       mc->init = sifive_u_machine_init;
>       mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT;
>       mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
> -    mc->default_cpu_type = SIFIVE_U_CPU;
> +    mc->default_cpu_type = sifive_u_cpu();
>       mc->default_cpus = mc->min_cpus;
>       mc->default_ram_id = "riscv.sifive.u.ram";
>       mc->auto_create_sdcard = true;
> @@ -764,7 +764,7 @@ static void sifive_u_soc_instance_init(Object *obj)
>                               TYPE_RISCV_HART_ARRAY);
>       qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
>       qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
> -    qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
> +    qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", sifive_e_cpu());
>       qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
>   
>       object_initialize_child(obj, "u-cluster", &s->u_cluster, TYPE_CPU_CLUSTER);
> 

Just inline and remove the header. With that:
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

Re: [PATCH 13/14] hw/riscv: Define SiFive E/U CPUs using runtime conditions

Posted by Philippe Mathieu-Daudé 13 hours ago

On 17/12/25 16:13, Philippe Mathieu-Daudé wrote:
> On 17/12/25 00:51, Anton Johansson wrote:
>> Signed-off-by: Anton Johansson <anjo@rev.ng>
>> ---
>>   include/hw/riscv/sifive_cpu.h | 26 +++++++++++++++++++-------
>>   hw/riscv/sifive_e.c           |  2 +-
>>   hw/riscv/sifive_u.c           |  4 ++--
>>   3 files changed, 22 insertions(+), 10 deletions(-)
>>
>> diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/ 
>> sifive_cpu.h
>> index 136799633a..8391141d5e 100644
>> --- a/include/hw/riscv/sifive_cpu.h
>> +++ b/include/hw/riscv/sifive_cpu.h
>> @@ -20,12 +20,24 @@
>>   #ifndef HW_SIFIVE_CPU_H
>>   #define HW_SIFIVE_CPU_H
>> -#if defined(TARGET_RISCV32)
>> -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31
>> -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34
>> -#elif defined(TARGET_RISCV64)
>> -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51
>> -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54
>> -#endif
>> +#include "qemu/target-info.h"
>> +
>> +static inline const char *sifive_e_cpu(void)
>> +{
>> +    if (target_riscv64()) {
>> +        return TYPE_RISCV_CPU_SIFIVE_E51;
>> +    } else {
>> +        return TYPE_RISCV_CPU_SIFIVE_E31;
>> +    }
>> +}
>> +
>> +static inline const char *sifive_u_cpu(void)
>> +{
>> +    if (target_riscv64()) {
>> +        return TYPE_RISCV_CPU_SIFIVE_U54;
>> +    } else {
>> +        return TYPE_RISCV_CPU_SIFIVE_U34;
>> +    }
>> +}
>>   #endif /* HW_SIFIVE_CPU_H */
>> diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c
>> index 7ed419cf69..458b21b9e3 100644
>> --- a/hw/riscv/sifive_e.c
>> +++ b/hw/riscv/sifive_e.c
>> @@ -151,7 +151,7 @@ static void 
>> sifive_e_machine_class_init(ObjectClass *oc, const void *data)
>>       mc->desc = "RISC-V Board compatible with SiFive E SDK";
>>       mc->init = sifive_e_machine_init;
>>       mc->max_cpus = 1;
>> -    mc->default_cpu_type = SIFIVE_E_CPU;
>> +    mc->default_cpu_type = sifive_e_cpu();
>>       mc->default_ram_id = "riscv.sifive.e.ram";
>>       mc->default_ram_size = sifive_e_memmap[SIFIVE_E_DEV_DTIM].size;
>> diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c
>> index 2ff2059bb9..a04481806e 100644
>> --- a/hw/riscv/sifive_u.c
>> +++ b/hw/riscv/sifive_u.c
>> @@ -723,7 +723,7 @@ static void 
>> sifive_u_machine_class_init(ObjectClass *oc, const void *data)
>>       mc->init = sifive_u_machine_init;
>>       mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 
>> SIFIVE_U_COMPUTE_CPU_COUNT;
>>       mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1;
>> -    mc->default_cpu_type = SIFIVE_U_CPU;
>> +    mc->default_cpu_type = sifive_u_cpu();
>>       mc->default_cpus = mc->min_cpus;
>>       mc->default_ram_id = "riscv.sifive.u.ram";
>>       mc->auto_create_sdcard = true;
>> @@ -764,7 +764,7 @@ static void sifive_u_soc_instance_init(Object *obj)
>>                               TYPE_RISCV_HART_ARRAY);
>>       qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1);
>>       qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0);
>> -    qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU);
>> +    qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", 
>> sifive_e_cpu());
>>       qdev_prop_set_uint64(DEVICE(&s->e_cpus), "resetvec", 0x1004);
>>       object_initialize_child(obj, "u-cluster", &s->u_cluster, 
>> TYPE_CPU_CLUSTER);
>>
> 
> Just inline and remove the header. With that:
> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>

If Alistair Acks the series and there is no other change requested,
I can address that cosmetic change myself, then no need to respin.
>

Re: [PATCH 13/14] hw/riscv: Define SiFive E/U CPUs using runtime conditions

Posted by Pierrick Bouvier 1 day, 7 hours ago

On 12/16/25 3:51 PM, Anton Johansson wrote:
> Signed-off-by: Anton Johansson <anjo@rev.ng>
> ---
>   include/hw/riscv/sifive_cpu.h | 26 +++++++++++++++++++-------
>   hw/riscv/sifive_e.c           |  2 +-
>   hw/riscv/sifive_u.c           |  4 ++--
>   3 files changed, 22 insertions(+), 10 deletions(-)
Reviewed-by: Pierrick Bouvier <pierrick.bouvier@linaro.org>