[v6] Basic ASID2 support

[PATCH v6 0/4] Basic ASID2 support

Jim MacArthur posted 4 patches 2 months ago

Diff against v1 v5
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20251210-jmac-asid2-v6-0-d3b3acab98c7@linaro.org

Maintainers: Peter Maydell <peter.maydell@linaro.org>

docs/system/arm/emulation.rst    |  1 +
target/arm/cpu-features.h        |  7 ++++
target/arm/cpu-sysregs.h.inc     |  1 +
target/arm/helper.c              | 32 ++++++++++++-----
target/arm/internals.h           |  5 +++
target/arm/tcg/cpu64.c           |  4 +++
tests/tcg/aarch64/system/asid2.c | 76 ++++++++++++++++++++++++++++++++++++++++
7 files changed, 118 insertions(+), 8 deletions(-)

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[PATCH v6 0/4] Basic ASID2 support

Posted by Jim MacArthur 2 months ago

Enable the ID_AA64MMFR4_EL1 register, add the ASID2 field for cpu_max,
then enable writes to FNG1, FNG0, and A2 bits of TCR2_EL1. Any change
of ASID still causes a TLB flush.

Changes since V5:

- Patch 2:
  - More specific TLB flush. Now only flushes the TLBs relevant to the
    written register, and then only if A2 changes.

Thanks to Richard Henderson for advice on TLB flushing.

Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>
---
Jim MacArthur (4):
      target/arm: Enable ID_AA64MMFR4_EL1 register
      target/arm: Allow writes to FNG1, FNG0, A2
      target/arm/tcg/cpu64.c: Enable ASID2 for cpu_max
      tests: Add test for ASID2 and write/read of feature bits

 docs/system/arm/emulation.rst    |  1 +
 target/arm/cpu-features.h        |  7 ++++
 target/arm/cpu-sysregs.h.inc     |  1 +
 target/arm/helper.c              | 32 ++++++++++++-----
 target/arm/internals.h           |  5 +++
 target/arm/tcg/cpu64.c           |  4 +++
 tests/tcg/aarch64/system/asid2.c | 76 ++++++++++++++++++++++++++++++++++++++++
 7 files changed, 118 insertions(+), 8 deletions(-)
---
base-commit: 9c23f2a7b0b45277693a14074b1aaa827eecdb92
change-id: 20251210-jmac-asid2-a82ba351478d

Best regards,
-- 
Jim MacArthur <jim.macarthur@linaro.org>

Re: [PATCH v6 0/4] Basic ASID2 support

Posted by Peter Maydell 3 weeks, 6 days ago

On Wed, 10 Dec 2025 at 14:51, Jim MacArthur <jim.macarthur@linaro.org> wrote:
>
> Enable the ID_AA64MMFR4_EL1 register, add the ASID2 field for cpu_max,
> then enable writes to FNG1, FNG0, and A2 bits of TCR2_EL1. Any change
> of ASID still causes a TLB flush.
>
> Changes since V5:
>
> - Patch 2:
>   - More specific TLB flush. Now only flushes the TLBs relevant to the
>     written register, and then only if A2 changes.
>
> Thanks to Richard Henderson for advice on TLB flushing.
>
> Signed-off-by: Jim MacArthur <jim.macarthur@linaro.org>
> ---
> Jim MacArthur (4):
>       target/arm: Enable ID_AA64MMFR4_EL1 register
>       target/arm: Allow writes to FNG1, FNG0, A2
>       target/arm/tcg/cpu64.c: Enable ASID2 for cpu_max
>       tests: Add test for ASID2 and write/read of feature bits

Applied to target-arm.next with the minor fixup on patch 1; thanks.

-- PMM