[v2] RISC-V: Initial support versioning of debug specification

[PATCH v2 0/2] RISC-V: Initial support versioning of debug specification

Alvin Chang via posted 2 patches 2 days, 17 hours ago

Diff against v1
Download series mbox

Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20251126164329.2157287-1-alvinga@andestech.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

target/riscv/cpu.c                |  1 +
target/riscv/cpu_cfg_fields.h.inc |  1 +
target/riscv/debug.c              | 56 +++++++++++++++++++++++++++++--
target/riscv/debug.h              |  1 +
4 files changed, 56 insertions(+), 3 deletions(-)

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[PATCH v2 0/2] RISC-V: Initial support versioning of debug specification

Posted by Alvin Chang via 2 days, 17 hours ago

This series try to support versioning of debug specification. The early debug
implementation supports debug specification v0.13, and later new trigger types
were added which are defined in debug specification v1.0 version. To support
both v0.13 and v1.0, we add 'debug-1.0' as CPU property to let user choose
debug specification v1.0 by specifying "debug-1.0=true". The default version is
still v0.13 if 'debug-1.0' is not provided and set.

For example, to enable debug specification v1.0 on max CPU:
1. -cpu max,debug-1.0=true

Changes since v1
- Apply suggestions from Daniel. Using boolean property instead of string.

Alvin Chang (2):
  target/riscv: Add "debug-1.0" to specify debug specification v1.0
  target/riscv: Simpily support versioning of debug trigger module

 target/riscv/cpu.c                |  1 +
 target/riscv/cpu_cfg_fields.h.inc |  1 +
 target/riscv/debug.c              | 56 +++++++++++++++++++++++++++++--
 target/riscv/debug.h              |  1 +
 4 files changed, 56 insertions(+), 3 deletions(-)

-- 
2.43.0