[v2] accel/tcg: Remove most MO_TE uses in cpu_ld/st_data()

[PATCH-for-11.0 v2 04/12] target/riscv: Use little-endian variant of cpu_ld/st_data*() for vector

Philippe Mathieu-Daudé posted 12 patches 2 months, 2 weeks ago

Diff against v1 v3
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Maintainers: Richard Henderson <richard.henderson@linaro.org>, Paolo Bonzini <pbonzini@redhat.com>, Laurent Vivier <laurent@vivier.eu>, Brian Cain <brian.cain@oss.qualcomm.com>, Helge Deller <deller@gmx.de>, Zhao Liu <zhao1.liu@intel.com>, Eduardo Habkost <eduardo@habkost.net>, "Philippe Mathieu-Daudé" <philmd@linaro.org>, Aurelien Jarno <aurelien@aurel32.net>, Jiaxun Yang <jiaxun.yang@flygoat.com>, Aleksandar Rikalo <arikalo@gmail.com>, Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Yoshinori Sato <yoshinori.sato@nifty.com>, Ilya Leoshkevich <iii@linux.ibm.com>, David Hildenbrand <david@kernel.org>, Thomas Huth <thuth@redhat.com>, Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>, Artyom Tarasenko <atar4qemu@gmail.com>, Bastian Koppelmann <kbastian@mail.uni-paderborn.de>

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[PATCH-for-11.0 v2 04/12] target/riscv: Use little-endian variant of cpu_ld/st_data*() for vector

Posted by Philippe Mathieu-Daudé 2 months, 2 weeks ago

RISC-V vector "elements are simply packed in order from
the least-signicant to most-signicant bits of the vector
register" [*] which is little endianness, therefore the
cpu_ld/st_data*() definitions expand to the little endian
declarations. Use the explicit little-endian variants.

[*] RISC-V "V" Vector Extension v1.0

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/riscv/vector_helper.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
index 2de3358ee86..caa8dd9c125 100644
--- a/target/riscv/vector_helper.c
+++ b/target/riscv/vector_helper.c
@@ -193,9 +193,9 @@ void NAME##_host(void *vd, uint32_t idx, void *host)        \
 }
 
 GEN_VEXT_LD_ELEM(lde_b, uint8_t,  H1, ldub)
-GEN_VEXT_LD_ELEM(lde_h, uint16_t, H2, lduw)
-GEN_VEXT_LD_ELEM(lde_w, uint32_t, H4, ldl)
-GEN_VEXT_LD_ELEM(lde_d, uint64_t, H8, ldq)
+GEN_VEXT_LD_ELEM(lde_h, uint16_t, H2, lduw_le)
+GEN_VEXT_LD_ELEM(lde_w, uint32_t, H4, ldl_le)
+GEN_VEXT_LD_ELEM(lde_d, uint64_t, H8, ldq_le)
 
 #define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF)             \
 static inline QEMU_ALWAYS_INLINE                            \
@@ -214,9 +214,9 @@ void NAME##_host(void *vd, uint32_t idx, void *host)        \
 }
 
 GEN_VEXT_ST_ELEM(ste_b, uint8_t,  H1, stb)
-GEN_VEXT_ST_ELEM(ste_h, uint16_t, H2, stw)
-GEN_VEXT_ST_ELEM(ste_w, uint32_t, H4, stl)
-GEN_VEXT_ST_ELEM(ste_d, uint64_t, H8, stq)
+GEN_VEXT_ST_ELEM(ste_h, uint16_t, H2, stw_le)
+GEN_VEXT_ST_ELEM(ste_w, uint32_t, H4, stl_le)
+GEN_VEXT_ST_ELEM(ste_d, uint64_t, H8, stq_le)
 
 static inline QEMU_ALWAYS_INLINE void
 vext_continuous_ldst_tlb(CPURISCVState *env, vext_ldst_elem_fn_tlb *ldst_tlb,
-- 
2.51.0

Re: [PATCH-for-11.0 v2 04/12] target/riscv: Use little-endian variant of cpu_ld/st_data*() for vector

Posted by Daniel Henrique Barboza 2 months, 2 weeks ago


On 11/26/25 4:49 AM, Philippe Mathieu-Daudé wrote:
> RISC-V vector "elements are simply packed in order from
> the least-signicant to most-signicant bits of the vector
> register" [*] which is little endianness, therefore the
> cpu_ld/st_data*() definitions expand to the little endian
> declarations. Use the explicit little-endian variants.
> 
> [*] RISC-V "V" Vector Extension v1.0
> 
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---


Reviewed-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>

>   target/riscv/vector_helper.c | 12 ++++++------
>   1 file changed, 6 insertions(+), 6 deletions(-)
> 
> diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c
> index 2de3358ee86..caa8dd9c125 100644
> --- a/target/riscv/vector_helper.c
> +++ b/target/riscv/vector_helper.c
> @@ -193,9 +193,9 @@ void NAME##_host(void *vd, uint32_t idx, void *host)        \
>   }
>   
>   GEN_VEXT_LD_ELEM(lde_b, uint8_t,  H1, ldub)
> -GEN_VEXT_LD_ELEM(lde_h, uint16_t, H2, lduw)
> -GEN_VEXT_LD_ELEM(lde_w, uint32_t, H4, ldl)
> -GEN_VEXT_LD_ELEM(lde_d, uint64_t, H8, ldq)
> +GEN_VEXT_LD_ELEM(lde_h, uint16_t, H2, lduw_le)
> +GEN_VEXT_LD_ELEM(lde_w, uint32_t, H4, ldl_le)
> +GEN_VEXT_LD_ELEM(lde_d, uint64_t, H8, ldq_le)
>   
>   #define GEN_VEXT_ST_ELEM(NAME, ETYPE, H, STSUF)             \
>   static inline QEMU_ALWAYS_INLINE                            \
> @@ -214,9 +214,9 @@ void NAME##_host(void *vd, uint32_t idx, void *host)        \
>   }
>   
>   GEN_VEXT_ST_ELEM(ste_b, uint8_t,  H1, stb)
> -GEN_VEXT_ST_ELEM(ste_h, uint16_t, H2, stw)
> -GEN_VEXT_ST_ELEM(ste_w, uint32_t, H4, stl)
> -GEN_VEXT_ST_ELEM(ste_d, uint64_t, H8, stq)
> +GEN_VEXT_ST_ELEM(ste_h, uint16_t, H2, stw_le)
> +GEN_VEXT_ST_ELEM(ste_w, uint32_t, H4, stl_le)
> +GEN_VEXT_ST_ELEM(ste_d, uint64_t, H8, stq_le)
>   
>   static inline QEMU_ALWAYS_INLINE void
>   vext_continuous_ldst_tlb(CPURISCVState *env, vext_ldst_elem_fn_tlb *ldst_tlb,