[v1] RISC-V: Initial support versioning of debug specification

[PATCH 0/2] RISC-V: Initial support versioning of debug specification

Alvin Chang via posted 2 patches 2 months, 1 week ago

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git fetch https://github.com/patchew-project/qemu tags/patchew/20251126071258.4132239-1-alvinga@andestech.com

Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>

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target/riscv/cpu.c         | 69 ++++++++++++++++++++++++++++++++++++++
target/riscv/cpu.h         | 13 +++++++
target/riscv/debug.c       | 61 +++++++++++++++++++++++++++++++--
target/riscv/debug.h       |  1 +
target/riscv/machine.c     |  5 +--
target/riscv/tcg/tcg-cpu.c |  3 ++
6 files changed, 147 insertions(+), 5 deletions(-)

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[PATCH 0/2] RISC-V: Initial support versioning of debug specification

Posted by Alvin Chang via 2 months, 1 week ago

This series try to support versioning of debug specification. The early debug
implementation supports debug specification v0.13, and later new trigger types
were added which are defined in debug specification v1.0 version. To support
both v0.13 and v1.0, we add 'debug_spec' into CPU option to let user select
intended version of the debug specification. The default version is v0.13.

For examples:
1. -cpu max,debug_spec=v0.13
2. -cpu max,debug_spec=v1.0

Alvin Chang (2):
  target/riscv: Add 'debug_ver' to set version of debug specification
  target/riscv: Simpily support versioning of debug infrastructure

 target/riscv/cpu.c         | 69 ++++++++++++++++++++++++++++++++++++++
 target/riscv/cpu.h         | 13 +++++++
 target/riscv/debug.c       | 61 +++++++++++++++++++++++++++++++--
 target/riscv/debug.h       |  1 +
 target/riscv/machine.c     |  5 +--
 target/riscv/tcg/tcg-cpu.c |  3 ++
 6 files changed, 147 insertions(+), 5 deletions(-)

-- 
2.43.0