accel/tcg: Remove most MO_TE uses in cpu_ld/st_code/data()

[RFC-PATCH-for-11.0 v3 10/21] target/hexagon: Use little-endian variant of cpu_ld/st_data*()

Posted by Philippe Mathieu-Daudé 2 months, 2 weeks ago

We only build the Hexagon target using little endianness order,
therefore the cpu_ld/st_data*() definitions expand to the little
endian declarations. Use the explicit little-endian variants.

Mechanical change running:

  $ tgt=hexagon; \
    end=le; \
    for op in data mmuidx_ra; do \
      for ac in uw sw l q; do \
        sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \
                  $(git grep -l cpu_ target/${tgt}/); \
      done;
      for ac in w l q; do \
        sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \
                  $(git grep -l cpu_ target/${tgt}/); \
      done;
    done

Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
---
 target/hexagon/macros.h    | 6 +++---
 target/hexagon/op_helper.c | 6 +++---
 2 files changed, 6 insertions(+), 6 deletions(-)

diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
index 088e5961ab7..6c2862a2320 100644
--- a/target/hexagon/macros.h
+++ b/target/hexagon/macros.h
@@ -519,9 +519,9 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv val, int shift)
 #define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA)
 #else
 #define MEM_LOAD1 cpu_ldub_data_ra
-#define MEM_LOAD2 cpu_lduw_data_ra
-#define MEM_LOAD4 cpu_ldl_data_ra
-#define MEM_LOAD8 cpu_ldq_data_ra
+#define MEM_LOAD2 cpu_lduw_le_data_ra
+#define MEM_LOAD4 cpu_ldl_le_data_ra
+#define MEM_LOAD8 cpu_ldq_le_data_ra
 
 #define fLOAD(NUM, SIZE, SIGN, EA, DST) \
     do { \
diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
index e2e80ca7efa..08db1e9c56b 100644
--- a/target/hexagon/op_helper.c
+++ b/target/hexagon/op_helper.c
@@ -77,13 +77,13 @@ static void commit_store(CPUHexagonState *env, int slot_num, uintptr_t ra)
         cpu_stb_data_ra(env, va, env->mem_log_stores[slot_num].data32, ra);
         break;
     case 2:
-        cpu_stw_data_ra(env, va, env->mem_log_stores[slot_num].data32, ra);
+        cpu_stw_le_data_ra(env, va, env->mem_log_stores[slot_num].data32, ra);
         break;
     case 4:
-        cpu_stl_data_ra(env, va, env->mem_log_stores[slot_num].data32, ra);
+        cpu_stl_le_data_ra(env, va, env->mem_log_stores[slot_num].data32, ra);
         break;
     case 8:
-        cpu_stq_data_ra(env, va, env->mem_log_stores[slot_num].data64, ra);
+        cpu_stq_le_data_ra(env, va, env->mem_log_stores[slot_num].data64, ra);
         break;
     default:
         g_assert_not_reached();
-- 
2.51.0

Re: [RFC-PATCH-for-11.0 v3 10/21] target/hexagon: Use little-endian variant of cpu_ld/st_data*()

Posted by Brian Cain 2 months, 2 weeks ago

On Fri, Nov 21, 2025 at 8:13 PM Philippe Mathieu-Daudé <philmd@linaro.org>
wrote:

> We only build the Hexagon target using little endianness order,
> therefore the cpu_ld/st_data*() definitions expand to the little
> endian declarations. Use the explicit little-endian variants.
>
> Mechanical change running:
>
>   $ tgt=hexagon; \
>     end=le; \
>     for op in data mmuidx_ra; do \
>       for ac in uw sw l q; do \
>         sed -i -e "s/cpu_ld${ac}_${op}/cpu_ld${ac}_${end}_${op}/" \
>                   $(git grep -l cpu_ target/${tgt}/); \
>       done;
>       for ac in w l q; do \
>         sed -i -e "s/cpu_st${ac}_${op}/cpu_st${ac}_${end}_${op}/" \
>                   $(git grep -l cpu_ target/${tgt}/); \
>       done;
>     done
>
> Signed-off-by: Philippe Mathieu-Daudé <philmd@linaro.org>
> ---
>

Reviewed-by: Brian Cain <brian.cain@oss.qualcomm.com>


>  target/hexagon/macros.h    | 6 +++---
>  target/hexagon/op_helper.c | 6 +++---
>  2 files changed, 6 insertions(+), 6 deletions(-)
>
> diff --git a/target/hexagon/macros.h b/target/hexagon/macros.h
> index 088e5961ab7..6c2862a2320 100644
> --- a/target/hexagon/macros.h
> +++ b/target/hexagon/macros.h
> @@ -519,9 +519,9 @@ static inline TCGv gen_read_ireg(TCGv result, TCGv
> val, int shift)
>  #define fLOAD(NUM, SIZE, SIGN, EA, DST) MEM_LOAD##SIZE##SIGN(DST, EA)
>  #else
>  #define MEM_LOAD1 cpu_ldub_data_ra
> -#define MEM_LOAD2 cpu_lduw_data_ra
> -#define MEM_LOAD4 cpu_ldl_data_ra
> -#define MEM_LOAD8 cpu_ldq_data_ra
> +#define MEM_LOAD2 cpu_lduw_le_data_ra
> +#define MEM_LOAD4 cpu_ldl_le_data_ra
> +#define MEM_LOAD8 cpu_ldq_le_data_ra
>
>  #define fLOAD(NUM, SIZE, SIGN, EA, DST) \
>      do { \
> diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c
> index e2e80ca7efa..08db1e9c56b 100644
> --- a/target/hexagon/op_helper.c
> +++ b/target/hexagon/op_helper.c
> @@ -77,13 +77,13 @@ static void commit_store(CPUHexagonState *env, int
> slot_num, uintptr_t ra)
>          cpu_stb_data_ra(env, va, env->mem_log_stores[slot_num].data32,
> ra);
>          break;
>      case 2:
> -        cpu_stw_data_ra(env, va, env->mem_log_stores[slot_num].data32,
> ra);
> +        cpu_stw_le_data_ra(env, va, env->mem_log_stores[slot_num].data32,
> ra);
>          break;
>      case 4:
> -        cpu_stl_data_ra(env, va, env->mem_log_stores[slot_num].data32,
> ra);
> +        cpu_stl_le_data_ra(env, va, env->mem_log_stores[slot_num].data32,
> ra);
>          break;
>      case 8:
> -        cpu_stq_data_ra(env, va, env->mem_log_stores[slot_num].data64,
> ra);
> +        cpu_stq_le_data_ra(env, va, env->mem_log_stores[slot_num].data64,
> ra);
>          break;
>      default:
>          g_assert_not_reached();
> --
> 2.51.0
>
>
>