Current DiamondRapids hasn't supported cache model. Instead, document
its special CPU & cache topology to allow user emulate with "-smp" &
"-machine smp-cache".
Cc: Yu Chen <yu.c.chen@intel.com>
Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
---
docs/system/cpu-models-x86.rst.inc | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/docs/system/cpu-models-x86.rst.inc b/docs/system/cpu-models-x86.rst.inc
index 6a770ca8351c..c4c8fc67a562 100644
--- a/docs/system/cpu-models-x86.rst.inc
+++ b/docs/system/cpu-models-x86.rst.inc
@@ -71,6 +71,26 @@ mixture of host CPU models between machines, if live migration
compatibility is required, use the newest CPU model that is compatible
across all desired hosts.
+``DiamondRapids``
+ Intel Xeon Processor.
+
+ Diamond Rapids product has a topology which differs from previous Xeon
+ products. It does not support SMT, but instead features a dual core
+ module (DCM) architecture. It also has core building blocks (CBB - die
+ level in CPU topology). The cache hierarchy is organized as follows:
+ L1 i/d cache is per thread, L2 cache is per DCM, and L3 cache is per
+ CBB. This cache topology can be emulated for DiamondRapids CPU model
+ using the smp-cache configuration as shown below:
+
+ Example:
+
+ ::
+
+ -machine smp-cache.0.cache=l1d,smp-cache.0.topology=thread,\
+ smp-cache.1.cache=l1i,smp-cache.1.topology=thread,\
+ smp-cache.2.cache=l2,smp-cache.2.topology=module,\
+ smp-cache.3.cache=l3,smp-cache.3.topology=die\
+
``ClearwaterForest``
Intel Xeon Processor (ClearwaterForest, 2025)
--
2.34.1In $SUBJECT s/dosc/docs/ On Thu, Nov 20, 2025 at 03:10:30PM +0800, Zhao Liu wrote: > Current DiamondRapids hasn't supported cache model. Instead, document > its special CPU & cache topology to allow user emulate with "-smp" & > "-machine smp-cache". > > Cc: Yu Chen <yu.c.chen@intel.com> > Signed-off-by: Zhao Liu <zhao1.liu@intel.com> > --- > docs/system/cpu-models-x86.rst.inc | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/docs/system/cpu-models-x86.rst.inc b/docs/system/cpu-models-x86.rst.inc > index 6a770ca8351c..c4c8fc67a562 100644 > --- a/docs/system/cpu-models-x86.rst.inc > +++ b/docs/system/cpu-models-x86.rst.inc > @@ -71,6 +71,26 @@ mixture of host CPU models between machines, if live migration > compatibility is required, use the newest CPU model that is compatible > across all desired hosts. > > +``DiamondRapids`` > + Intel Xeon Processor. > + > + Diamond Rapids product has a topology which differs from previous Xeon > + products. It does not support SMT, but instead features a dual core > + module (DCM) architecture. It also has core building blocks (CBB - die > + level in CPU topology). The cache hierarchy is organized as follows: > + L1 i/d cache is per thread, L2 cache is per DCM, and L3 cache is per > + CBB. This cache topology can be emulated for DiamondRapids CPU model > + using the smp-cache configuration as shown below: > + > + Example: > + > + :: > + > + -machine smp-cache.0.cache=l1d,smp-cache.0.topology=thread,\ > + smp-cache.1.cache=l1i,smp-cache.1.topology=thread,\ > + smp-cache.2.cache=l2,smp-cache.2.topology=module,\ > + smp-cache.3.cache=l3,smp-cache.3.topology=die\ > + > ``ClearwaterForest`` > Intel Xeon Processor (ClearwaterForest, 2025) > > -- > 2.34.1 > With regards, Daniel -- |: https://berrange.com -o- https://www.flickr.com/photos/dberrange :| |: https://libvirt.org -o- https://fstop138.berrange.com :| |: https://entangle-photo.org -o- https://www.instagram.com/dberrange :|
On Tue, Jan 06, 2026 at 11:22:05AM +0000, Daniel P. Berrangé wrote: > Date: Tue, 6 Jan 2026 11:22:05 +0000 > From: "Daniel P. Berrangé" <berrange@redhat.com> > Subject: Re: [PATCH 10/10] dosc/cpu-models-x86: Add documentation for > DiamondRapids > > In $SUBJECT s/dosc/docs/ Yeah, thanks! (Since this patch has been merged, I'll be more careful next. :-)) -Zhao
On Thu, Nov 20, 2025 at 03:10:30PM +0800, Zhao Liu wrote:
> Current DiamondRapids hasn't supported cache model. Instead, document
> its special CPU & cache topology to allow user emulate with "-smp" &
> "-machine smp-cache".
>
> Cc: Yu Chen <yu.c.chen@intel.com>
> Signed-off-by: Zhao Liu <zhao1.liu@intel.com>
> ---
> docs/system/cpu-models-x86.rst.inc | 20 ++++++++++++++++++++
> 1 file changed, 20 insertions(+)
>
> diff --git a/docs/system/cpu-models-x86.rst.inc b/docs/system/cpu-models-x86.rst.inc
> index 6a770ca8351c..c4c8fc67a562 100644
> --- a/docs/system/cpu-models-x86.rst.inc
> +++ b/docs/system/cpu-models-x86.rst.inc
> @@ -71,6 +71,26 @@ mixture of host CPU models between machines, if live migration
> compatibility is required, use the newest CPU model that is compatible
> across all desired hosts.
>
> +``DiamondRapids``
> + Intel Xeon Processor.
> +
> + Diamond Rapids product has a topology which differs from previous Xeon
> + products. It does not support SMT, but instead features a dual core
> + module (DCM) architecture. It also has core building blocks (CBB - die
> + level in CPU topology). The cache hierarchy is organized as follows:
> + L1 i/d cache is per thread, L2 cache is per DCM, and L3 cache is per
> + CBB. This cache topology can be emulated for DiamondRapids CPU model
> + using the smp-cache configuration as shown below:
Can I request a slight rewording to simplify this:
``DiamondRapids``
Intel Xeon Processor (DiamondRapids, 2025). This does not include SMT
but allows the module and die topology levels. The cache hierarchy is
L1 i/d cache per thread, L2 cache per module, and L3 cache per die,
which can be emulated using using the smp-cache option:
Example:
::
-machine smp-cache.0.cache=l1d,smp-cache.0.topology=thread,\
smp-cache.1.cache=l1i,smp-cache.1.topology=thread,\
smp-cache.2.cache=l2,smp-cache.2.topology=module,\
smp-cache.3.cache=l3,smp-cache.3.topology=die,\
...
With regards,
Daniel
--
|: https://berrange.com -o- https://www.flickr.com/photos/dberrange :|
|: https://libvirt.org -o- https://fstop138.berrange.com :|
|: https://entangle-photo.org -o- https://www.instagram.com/dberrange :|
Hi Daniel, > > +``DiamondRapids`` > > + Intel Xeon Processor. > > + > > + Diamond Rapids product has a topology which differs from previous Xeon > > + products. It does not support SMT, but instead features a dual core > > + module (DCM) architecture. It also has core building blocks (CBB - die > > + level in CPU topology). The cache hierarchy is organized as follows: > > + L1 i/d cache is per thread, L2 cache is per DCM, and L3 cache is per > > + CBB. This cache topology can be emulated for DiamondRapids CPU model > > + using the smp-cache configuration as shown below: > > Can I request a slight rewording to simplify this: Yes, of course. > ``DiamondRapids`` > Intel Xeon Processor (DiamondRapids, 2025). This does not include SMT > but allows the module and die topology levels. The cache hierarchy is > L1 i/d cache per thread, L2 cache per module, and L3 cache per die, > which can be emulated using using the smp-cache option: Thanks for your words! In the previous text, I also aimed to clarify the relationship between DCM/CBB and the QEMU topology hierarchy, as these terms appear frequently in DMR-related materials. Therefore, I thought a brief explanation of DCM/CBB may be helpful: This does not include SMT but allows the module (dual core module - DCM) and die (core building block - CBB) topology levels. What do you think? > Example: > > :: > > -machine smp-cache.0.cache=l1d,smp-cache.0.topology=thread,\ > smp-cache.1.cache=l1i,smp-cache.1.topology=thread,\ > smp-cache.2.cache=l2,smp-cache.2.topology=module,\ > smp-cache.3.cache=l3,smp-cache.3.topology=die,\ > ... Thanks, Zhao
Hi Daniel, just a gentle poke. Thanks, Zhao On Wed, Jan 07, 2026 at 11:42:27AM +0800, Zhao Liu wrote: > Date: Wed, 7 Jan 2026 11:42:27 +0800 > From: Zhao Liu <zhao1.liu@intel.com> > Subject: Re: [PATCH 10/10] dosc/cpu-models-x86: Add documentation for > DiamondRapids > > Hi Daniel, > > > > +``DiamondRapids`` > > > + Intel Xeon Processor. > > > + > > > + Diamond Rapids product has a topology which differs from previous Xeon > > > + products. It does not support SMT, but instead features a dual core > > > + module (DCM) architecture. It also has core building blocks (CBB - die > > > + level in CPU topology). The cache hierarchy is organized as follows: > > > + L1 i/d cache is per thread, L2 cache is per DCM, and L3 cache is per > > > + CBB. This cache topology can be emulated for DiamondRapids CPU model > > > + using the smp-cache configuration as shown below: > > > > Can I request a slight rewording to simplify this: > > Yes, of course. > > > ``DiamondRapids`` > > Intel Xeon Processor (DiamondRapids, 2025). This does not include SMT > > but allows the module and die topology levels. The cache hierarchy is > > L1 i/d cache per thread, L2 cache per module, and L3 cache per die, > > which can be emulated using using the smp-cache option: > > Thanks for your words! > > In the previous text, I also aimed to clarify the relationship between > DCM/CBB and the QEMU topology hierarchy, as these terms appear frequently > in DMR-related materials. Therefore, I thought a brief explanation of > DCM/CBB may be helpful: > > This does not include SMT but allows the module (dual core module - DCM) > and die (core building block - CBB) topology levels. > > What do you think? > > > > Example: > > > > :: > > > > -machine smp-cache.0.cache=l1d,smp-cache.0.topology=thread,\ > > smp-cache.1.cache=l1i,smp-cache.1.topology=thread,\ > > smp-cache.2.cache=l2,smp-cache.2.topology=module,\ > > smp-cache.3.cache=l3,smp-cache.3.topology=die,\ > > ... > > Thanks, > Zhao >
On 11/20/2025 3:10 PM, Zhao Liu wrote: > Current DiamondRapids hasn't supported cache model. Instead, document > its special CPU & cache topology to allow user emulate with "-smp" & > "-machine smp-cache". > > Cc: Yu Chen <yu.c.chen@intel.com> > Signed-off-by: Zhao Liu <zhao1.liu@intel.com> > --- Reviewed-by: Chen Yu <yu.c.chen@intel.com> thanks, Chenyu > docs/system/cpu-models-x86.rst.inc | 20 ++++++++++++++++++++ > 1 file changed, 20 insertions(+) > > diff --git a/docs/system/cpu-models-x86.rst.inc b/docs/system/cpu-models-x86.rst.inc > index 6a770ca8351c..c4c8fc67a562 100644 > --- a/docs/system/cpu-models-x86.rst.inc > +++ b/docs/system/cpu-models-x86.rst.inc > @@ -71,6 +71,26 @@ mixture of host CPU models between machines, if live migration > compatibility is required, use the newest CPU model that is compatible > across all desired hosts. > > +``DiamondRapids`` > + Intel Xeon Processor. > + > + Diamond Rapids product has a topology which differs from previous Xeon > + products. It does not support SMT, but instead features a dual core > + module (DCM) architecture. It also has core building blocks (CBB - die > + level in CPU topology). The cache hierarchy is organized as follows: > + L1 i/d cache is per thread, L2 cache is per DCM, and L3 cache is per > + CBB. This cache topology can be emulated for DiamondRapids CPU model > + using the smp-cache configuration as shown below: > + > + Example: > + > + :: > + > + -machine smp-cache.0.cache=l1d,smp-cache.0.topology=thread,\ > + smp-cache.1.cache=l1i,smp-cache.1.topology=thread,\ > + smp-cache.2.cache=l2,smp-cache.2.topology=module,\ > + smp-cache.3.cache=l3,smp-cache.3.topology=die\ > + > ``ClearwaterForest`` > Intel Xeon Processor (ClearwaterForest, 2025) >
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