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[PATCH v14 00/14] riscv: Add support for MIPS P8700 CPU

Djordje Todorovic posted 14 patches 2 months, 2 weeks ago
Patches applied successfully (tree, apply log)
git fetch https://github.com/patchew-project/qemu tags/patchew/20251118085758.3996513-1-djordje.todorovic@htecgroup.com
Maintainers: Palmer Dabbelt <palmer@dabbelt.com>, Alistair Francis <alistair.francis@wdc.com>, Weiwei Li <liwei1518@gmail.com>, Daniel Henrique Barboza <dbarboza@ventanamicro.com>, Liu Zhiwei <zhiwei_liu@linux.alibaba.com>, Paolo Bonzini <pbonzini@redhat.com>
There is a newer version of this series
configs/devices/riscv64-softmmu/default.mak |   1 +
docs/system/riscv/mips.rst                  |  20 +
docs/system/target-riscv.rst                |   1 +
hw/intc/riscv_aclint.c                      |  18 +-
hw/intc/riscv_aplic.c                       |  13 +-
hw/misc/Kconfig                             |  17 +
hw/misc/meson.build                         |   3 +
hw/misc/riscv_cmgcr.c                       | 243 ++++++++++
hw/misc/riscv_cpc.c                         | 265 +++++++++++
hw/riscv/Kconfig                            |   6 +
hw/riscv/boston-aia.c                       | 476 ++++++++++++++++++++
hw/riscv/cps.c                              | 196 ++++++++
hw/riscv/meson.build                        |   3 +
include/hw/misc/riscv_cmgcr.h               |  48 ++
include/hw/misc/riscv_cpc.h                 |  64 +++
include/hw/riscv/cps.h                      |  66 +++
scripts/checkpatch.pl                       |   4 +
target/riscv/cpu-qom.h                      |   1 +
target/riscv/cpu.c                          |  44 ++
target/riscv/cpu.h                          |   7 +
target/riscv/cpu_cfg.h                      |   5 +
target/riscv/cpu_cfg_fields.h.inc           |   3 +
target/riscv/cpu_vendorid.h                 |   1 +
target/riscv/insn_trans/trans_xmips.c.inc   | 136 ++++++
target/riscv/meson.build                    |   2 +
target/riscv/mips_csr.c                     | 217 +++++++++
target/riscv/translate.c                    |   3 +
target/riscv/xmips.decode                   |  35 ++
tests/functional/riscv64/meson.build        |   2 +
tests/functional/riscv64/test_boston.py     | 123 +++++
30 files changed, 2018 insertions(+), 5 deletions(-)
create mode 100644 docs/system/riscv/mips.rst
create mode 100644 hw/misc/riscv_cmgcr.c
create mode 100644 hw/misc/riscv_cpc.c
create mode 100644 hw/riscv/boston-aia.c
create mode 100644 hw/riscv/cps.c
create mode 100644 include/hw/misc/riscv_cmgcr.h
create mode 100644 include/hw/misc/riscv_cpc.h
create mode 100644 include/hw/riscv/cps.h
create mode 100644 target/riscv/insn_trans/trans_xmips.c.inc
create mode 100644 target/riscv/mips_csr.c
create mode 100644 target/riscv/xmips.decode
create mode 100755 tests/functional/riscv64/test_boston.py
[PATCH v14 00/14] riscv: Add support for MIPS P8700 CPU
Posted by Djordje Todorovic 2 months, 2 weeks ago 
Address several things:

- Move boston test to thorough group
- Add check for DEVICE_NATIVE_ENDIAN in checkpatch.pl
- Avoid DEVICE_NATIVE_ENDIAN in CMGCR

Djordje Todorovic (14):
  hw/intc: Allow gaps in hartids for aclint and aplic
  target/riscv: Add cpu_set_exception_base
  target/riscv: Add MIPS P8700 CPU
  target/riscv: Add MIPS P8700 CSRs
  target/riscv: Add mips.ccmov instruction
  target/riscv: Add mips.pref instruction
  target/riscv: Add Xmipslsp instructions
  hw/misc: Add RISC-V CMGCR device implementation
  hw/misc: Add RISC-V CPC device implementation
  hw/riscv: Add support for RISCV CPS
  hw/riscv: Add support for MIPS Boston-aia board mode
  riscv/boston-aia: Add an e1000e NIC in slot 0 func 1
  test/functional: Add test for boston-aia board
  scripts/checkpatch: Check DEVICE_NATIVE_ENDIAN

 configs/devices/riscv64-softmmu/default.mak |   1 +
 docs/system/riscv/mips.rst                  |  20 +
 docs/system/target-riscv.rst                |   1 +
 hw/intc/riscv_aclint.c                      |  18 +-
 hw/intc/riscv_aplic.c                       |  13 +-
 hw/misc/Kconfig                             |  17 +
 hw/misc/meson.build                         |   3 +
 hw/misc/riscv_cmgcr.c                       | 243 ++++++++++
 hw/misc/riscv_cpc.c                         | 265 +++++++++++
 hw/riscv/Kconfig                            |   6 +
 hw/riscv/boston-aia.c                       | 476 ++++++++++++++++++++
 hw/riscv/cps.c                              | 196 ++++++++
 hw/riscv/meson.build                        |   3 +
 include/hw/misc/riscv_cmgcr.h               |  48 ++
 include/hw/misc/riscv_cpc.h                 |  64 +++
 include/hw/riscv/cps.h                      |  66 +++
 scripts/checkpatch.pl                       |   4 +
 target/riscv/cpu-qom.h                      |   1 +
 target/riscv/cpu.c                          |  44 ++
 target/riscv/cpu.h                          |   7 +
 target/riscv/cpu_cfg.h                      |   5 +
 target/riscv/cpu_cfg_fields.h.inc           |   3 +
 target/riscv/cpu_vendorid.h                 |   1 +
 target/riscv/insn_trans/trans_xmips.c.inc   | 136 ++++++
 target/riscv/meson.build                    |   2 +
 target/riscv/mips_csr.c                     | 217 +++++++++
 target/riscv/translate.c                    |   3 +
 target/riscv/xmips.decode                   |  35 ++
 tests/functional/riscv64/meson.build        |   2 +
 tests/functional/riscv64/test_boston.py     | 123 +++++
 30 files changed, 2018 insertions(+), 5 deletions(-)
 create mode 100644 docs/system/riscv/mips.rst
 create mode 100644 hw/misc/riscv_cmgcr.c
 create mode 100644 hw/misc/riscv_cpc.c
 create mode 100644 hw/riscv/boston-aia.c
 create mode 100644 hw/riscv/cps.c
 create mode 100644 include/hw/misc/riscv_cmgcr.h
 create mode 100644 include/hw/misc/riscv_cpc.h
 create mode 100644 include/hw/riscv/cps.h
 create mode 100644 target/riscv/insn_trans/trans_xmips.c.inc
 create mode 100644 target/riscv/mips_csr.c
 create mode 100644 target/riscv/xmips.decode
 create mode 100755 tests/functional/riscv64/test_boston.py

-- 
2.34.1
Re: [PATCH v14 00/14] riscv: Add support for MIPS P8700 CPU
Posted by Djordje Todorovic 2 months ago 
Hi all,

What is the status for this? :)

Best regards,

Djordje


On 18. 11. 25. 09:58, Djordje Todorovic wrote:
> Address several things:
>
> - Move boston test to thorough group
> - Add check for DEVICE_NATIVE_ENDIAN in checkpatch.pl
> - Avoid DEVICE_NATIVE_ENDIAN in CMGCR
>
> Djordje Todorovic (14):
>    hw/intc: Allow gaps in hartids for aclint and aplic
>    target/riscv: Add cpu_set_exception_base
>    target/riscv: Add MIPS P8700 CPU
>    target/riscv: Add MIPS P8700 CSRs
>    target/riscv: Add mips.ccmov instruction
>    target/riscv: Add mips.pref instruction
>    target/riscv: Add Xmipslsp instructions
>    hw/misc: Add RISC-V CMGCR device implementation
>    hw/misc: Add RISC-V CPC device implementation
>    hw/riscv: Add support for RISCV CPS
>    hw/riscv: Add support for MIPS Boston-aia board mode
>    riscv/boston-aia: Add an e1000e NIC in slot 0 func 1
>    test/functional: Add test for boston-aia board
>    scripts/checkpatch: Check DEVICE_NATIVE_ENDIAN
>
>   configs/devices/riscv64-softmmu/default.mak |   1 +
>   docs/system/riscv/mips.rst                  |  20 +
>   docs/system/target-riscv.rst                |   1 +
>   hw/intc/riscv_aclint.c                      |  18 +-
>   hw/intc/riscv_aplic.c                       |  13 +-
>   hw/misc/Kconfig                             |  17 +
>   hw/misc/meson.build                         |   3 +
>   hw/misc/riscv_cmgcr.c                       | 243 ++++++++++
>   hw/misc/riscv_cpc.c                         | 265 +++++++++++
>   hw/riscv/Kconfig                            |   6 +
>   hw/riscv/boston-aia.c                       | 476 ++++++++++++++++++++
>   hw/riscv/cps.c                              | 196 ++++++++
>   hw/riscv/meson.build                        |   3 +
>   include/hw/misc/riscv_cmgcr.h               |  48 ++
>   include/hw/misc/riscv_cpc.h                 |  64 +++
>   include/hw/riscv/cps.h                      |  66 +++
>   scripts/checkpatch.pl                       |   4 +
>   target/riscv/cpu-qom.h                      |   1 +
>   target/riscv/cpu.c                          |  44 ++
>   target/riscv/cpu.h                          |   7 +
>   target/riscv/cpu_cfg.h                      |   5 +
>   target/riscv/cpu_cfg_fields.h.inc           |   3 +
>   target/riscv/cpu_vendorid.h                 |   1 +
>   target/riscv/insn_trans/trans_xmips.c.inc   | 136 ++++++
>   target/riscv/meson.build                    |   2 +
>   target/riscv/mips_csr.c                     | 217 +++++++++
>   target/riscv/translate.c                    |   3 +
>   target/riscv/xmips.decode                   |  35 ++
>   tests/functional/riscv64/meson.build        |   2 +
>   tests/functional/riscv64/test_boston.py     | 123 +++++
>   30 files changed, 2018 insertions(+), 5 deletions(-)
>   create mode 100644 docs/system/riscv/mips.rst
>   create mode 100644 hw/misc/riscv_cmgcr.c
>   create mode 100644 hw/misc/riscv_cpc.c
>   create mode 100644 hw/riscv/boston-aia.c
>   create mode 100644 hw/riscv/cps.c
>   create mode 100644 include/hw/misc/riscv_cmgcr.h
>   create mode 100644 include/hw/misc/riscv_cpc.h
>   create mode 100644 include/hw/riscv/cps.h
>   create mode 100644 target/riscv/insn_trans/trans_xmips.c.inc
>   create mode 100644 target/riscv/mips_csr.c
>   create mode 100644 target/riscv/xmips.decode
>   create mode 100755 tests/functional/riscv64/test_boston.py
>
Re: [PATCH v14 00/14] riscv: Add support for MIPS P8700 CPU
Posted by Philippe Mathieu-Daudé 2 months ago 
Hi,

On 3/12/25 12:24, Djordje Todorovic wrote:
> Hi all,
> 
> What is the status for this? :)

Series looks OK for being queued by Alistair (RISC-V tree).
QEMU tree is now freezed until the next release (v10.2.0).
We now all wait the tree to re-open for development...

Regards,

Phil.

> 
> Best regards,
> 
> Djordje
Re: [PATCH v14 00/14] riscv: Add support for MIPS P8700 CPU
Posted by Djordje Todorovic 2 months ago 
Hi,

Thanks a lot for the feedback!

Djordje


On 3. 12. 25. 12:53, Philippe Mathieu-Daudé wrote:
> CAUTION: This email originated from outside of the organization. Do 
> not click links or open attachments unless you recognize the sender 
> and know the content is safe.
>
>
> Hi,
>
> On 3/12/25 12:24, Djordje Todorovic wrote:
>> Hi all,
>>
>> What is the status for this? :)
>
> Series looks OK for being queued by Alistair (RISC-V tree).
> QEMU tree is now freezed until the next release (v10.2.0).
> We now all wait the tree to re-open for development...
>
> Regards,
>
> Phil.
>
>>
>> Best regards,
>>
>> Djordje

Patchew 2.1-devel-b67e4c2

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