On 11/20/25 9:14 AM, Konstantin Semichastnov wrote:
>
>
> On 11/11/25 14:46, Daniel Henrique Barboza wrote:
>> Hi,
>>
>> In this v2 we're addressing a review comment from Konstantin in patch
>> 14. We're also doing changes in the FDT (patch 5) to keep up with the
>> changes that the kernel support is making [1].
>>
>> I've been thinking about adding partial support for N-trace in this work
>> as well. From what I can tell the difference between N-trace and E-trace
>> are the encoding of the packages, with everything else staying the same.
>> In this case we could add hooks in the code to be ready to support
>> N-trace encoding in the future.
>>
>> No other changes made. Patches based on current master.
>>
>> Changes in v2:
>> - patch 5:
>> - changed tr_compat from "ventana,veyron-v2-trace" to "qemu,trace-component"
>> - renamed trace encoder prop handler "cpu" to "cpus"
>> - patch 14:
>> - removed updiscon generation in gen_jal()
>> - v1 link: https://lore.kernel.org/qemu-riscv/20251002112335.2374517-1-dbarboza@ventanamicro.com/
>>
>>
>> [1] https://lore.kernel.org/linux-riscv/20251101154245.162492-1-apatel@ventanamicro.com/
>>
>> Daniel Henrique Barboza (16):
>> hw/riscv: Trace Encoder initial impl
>> hw/riscv: Trace RAM Sink initial impl
>> hw/riscv/trace-encoder: add trace start/stop logic
>> hw/riscv/virt.c: add trace encoders and trace ram sinks
>> hw/riscv: add e-trace message helpers
>> target/riscv: add initial trace instrumentation
>> hw/riscv/trace-encoder: write e-trace packets to RAM sink
>> test/qtest: add riscv-trace-test.c
>> hw/riscv/rv-trace-messages.c: add encoded trap message
>> hw/riscv, target/riscv: send trace trap messages
>> target/riscv, hw/riscv: send trace ppccd packets
>> hw/riscv/trace: add format2 msg helper
>> hw/riscv, target/riscv: send resync updiscon trace packets
>> hw/riscv/rv-trace-messages: add format 1 msgs with branch info
>> hw/riscv/trace-encoder: send branches info
>> hw/riscv/trace: update branch bit in sync messages
>>
>> Mayuresh Chitale (1):
>> hw/riscv/virt.c add trace encoder and ramsink fdt nodes
>>
>> hw/riscv/Kconfig | 5 +
>> hw/riscv/meson.build | 2 +
>> hw/riscv/rv-trace-messages.c | 373 +++++++++++
>> hw/riscv/rv-trace-messages.h | 40 ++
>> hw/riscv/trace-encoder.c | 609 ++++++++++++++++++
>> hw/riscv/trace-encoder.h | 62 ++
>> hw/riscv/trace-events | 9 +
>> hw/riscv/trace-ram-sink.c | 263 ++++++++
>> hw/riscv/trace-ram-sink.h | 83 +++
>> hw/riscv/virt.c | 135 ++++
>> include/hw/riscv/virt.h | 2 +
>> target/riscv/cpu.h | 11 +
>> target/riscv/cpu_helper.c | 26 +-
>> target/riscv/helper.h | 6 +
>> .../riscv/insn_trans/trans_privileged.c.inc | 11 +
>> target/riscv/insn_trans/trans_rvi.c.inc | 15 +
>> target/riscv/meson.build | 3 +-
>> target/riscv/tcg/tcg-cpu.c | 5 +
>> target/riscv/trace_helper.c | 62 ++
>> target/riscv/translate.c | 19 +
>> tests/qtest/meson.build | 2 +-
>> tests/qtest/riscv-trace-test.c | 120 ++++
>> 22 files changed, 1860 insertions(+), 3 deletions(-)
>> create mode 100644 hw/riscv/rv-trace-messages.c
>> create mode 100644 hw/riscv/rv-trace-messages.h
>> create mode 100644 hw/riscv/trace-encoder.c
>> create mode 100644 hw/riscv/trace-encoder.h
>> create mode 100644 hw/riscv/trace-ram-sink.c
>> create mode 100644 hw/riscv/trace-ram-sink.h
>> create mode 100644 target/riscv/trace_helper.c
>> create mode 100644 tests/qtest/riscv-trace-test.c
>>
> Hi, I am currently working on adding the N-Trace message format, based on your v1 patch set. Currently I have supported ProgTraceSync, ProgTraceCorrelation, ResourceFull, IndirectBranchHist, IndirectBranchHistSync, Ownership messages.
>
> After finishing the internal review and rebasing over the v2 patch set, I would like to send it here next week.
That's awesome! Let me know if you need any change to be made in this base series
to properly support N-trace.
Thanks,
Daniel
>
> Konstantin