From: YannickV <Y.Vossen@beckhoff.com>
The A9 global timer and ARM MP timer use PERIPHCLK as
their clock source. The frequency of PERIPHCLK is derived
by dividing the main clock (CLK) by a configurable
divider (must be at least 2). Previously, the PERIPHCLK
divider was not configurable, which could lead to
unexspected behavior if the application exspected a
different PERIPHCLK rate.
The property periphclk-divider specifies by which value
the main clock is divided to generate PERIPHCLK. This
allows flexible configuration of the timer clocks to
match application requirements.
Information can be found in the Zynq 7000 Soc Technical
Reference Manual under Timers.
https://docs.amd.com/r/en-US/ug585-zynq-7000-SoC-TRM
Signed-off-by: YannickV <Y.Vossen@beckhoff.com>
---
hw/timer/a9gtimer.c | 19 ++++++++++++++++++-
hw/timer/arm_mptimer.c | 19 ++++++++++++++++++-
include/hw/timer/a9gtimer.h | 1 +
include/hw/timer/arm_mptimer.h | 2 ++
4 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/hw/timer/a9gtimer.c b/hw/timer/a9gtimer.c
index 090d14c683..31eb9422f7 100644
--- a/hw/timer/a9gtimer.c
+++ b/hw/timer/a9gtimer.c
@@ -27,6 +27,7 @@
#include "hw/timer/a9gtimer.h"
#include "migration/vmstate.h"
#include "qapi/error.h"
+#include "qemu/error-report.h"
#include "qemu/timer.h"
#include "qemu/bitops.h"
#include "qemu/log.h"
@@ -62,9 +63,17 @@ static inline int a9_gtimer_get_current_cpu(A9GTimerState *s)
static inline uint64_t a9_gtimer_get_conv(A9GTimerState *s)
{
+ /*
+ * Referring to the ARM-Cortex-A9 MPCore TRM
+ *
+ * The a9 global timer relies on the PERIPHCLK as its clock source.
+ * The PERIPHCLK clock period must be configured as a multiple of the
+ * main clock CLK. The conversion from the qemu clock (1GHz) to a9
+ * gtimer ticks can be calculated like this:
+ */
uint64_t prescale = extract32(s->control, R_CONTROL_PRESCALER_SHIFT,
R_CONTROL_PRESCALER_LEN) + 1;
- uint64_t scaled_prescaler = prescale * 10;
+ uint64_t scaled_prescaler = prescale * s->periphclk_divider;
return muldiv64(scaled_prescaler, NANOSECONDS_PER_SECOND, s->freq_hz);
}
@@ -312,6 +321,12 @@ static void a9_gtimer_realize(DeviceState *dev, Error **errp)
sysbus_init_mmio(sbd, &s->iomem);
s->timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, a9_gtimer_update_no_sync, s);
+ if (s->periphclk_divider < 2) {
+ error_setg(errp, "Invalid periphclk-divider (%lu), must be >= 2",
+ s->periphclk_divider);
+ return;
+ }
+
for (i = 0; i < s->num_cpu; i++) {
A9GTimerPerCPU *gtb = &s->per_cpu[i];
@@ -378,6 +393,8 @@ static const Property a9_gtimer_properties[] = {
DEFINE_PROP_UINT64("clock-frequency", A9GTimerState, freq_hz,
NANOSECONDS_PER_SECOND),
DEFINE_PROP_UINT32("num-cpu", A9GTimerState, num_cpu, 0),
+ DEFINE_PROP_UINT64("periphclk-divider", A9GTimerState,
+ periphclk_divider, 10),
};
static void a9_gtimer_class_init(ObjectClass *klass, void *data)
diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c
index cae07090f9..a7434cf56a 100644
--- a/hw/timer/arm_mptimer.c
+++ b/hw/timer/arm_mptimer.c
@@ -27,6 +27,7 @@
#include "hw/timer/arm_mptimer.h"
#include "migration/vmstate.h"
#include "qapi/error.h"
+#include "qemu/error-report.h"
#include "qemu/module.h"
#include "hw/core/cpu.h"
@@ -61,8 +62,16 @@ static inline void timerblock_update_irq(TimerBlock *tb)
/* Return conversion factor from mpcore timer ticks to qemu timer ticks. */
static inline uint32_t timerblock_scale(TimerBlock *tb, uint32_t control)
{
+ /*
+ * Referring to the ARM-Cortex-A9 MPCore TRM
+ *
+ * The arm mp timer relies on the PERIPHCLK as its clock source.
+ * The PERIPHCLK clock period must be configured as a multiple of the
+ * main clock CLK. The conversion from the qemu clock (1GHz) to arm mp
+ * timer ticks can be calculated like this:
+ */
uint64_t prescale = (((control >> 8) & 0xff) + 1);
- uint64_t scaled_prescaler = prescale * 10;
+ uint64_t scaled_prescaler = prescale * tb->periphclk_divider;
return muldiv64(scaled_prescaler, NANOSECONDS_PER_SECOND, tb->freq_hz);
}
@@ -273,6 +282,12 @@ static void arm_mptimer_realize(DeviceState *dev, Error **errp)
for (i = 0; i < s->num_cpu; i++) {
TimerBlock *tb = &s->timerblock[i];
tb->freq_hz = s->freq_hz;
+ if (s->periphclk_divider < 2) {
+ error_setg(errp, "Invalid periphclk-divider (%lu), must be >= 2",
+ s->periphclk_divider);
+ return;
+ }
+ tb->periphclk_divider = s->periphclk_divider;
tb->timer = ptimer_init(timerblock_tick, tb, PTIMER_POLICY);
sysbus_init_irq(sbd, &tb->irq);
memory_region_init_io(&tb->iomem, OBJECT(s), &timerblock_ops, tb,
@@ -309,6 +324,8 @@ static const Property arm_mptimer_properties[] = {
DEFINE_PROP_UINT64("clock-frequency", ARMMPTimerState, freq_hz,
NANOSECONDS_PER_SECOND),
DEFINE_PROP_UINT32("num-cpu", ARMMPTimerState, num_cpu, 0),
+ DEFINE_PROP_UINT64("periphclk-divider", ARMMPTimerState,
+ periphclk_divider, 10),
};
static void arm_mptimer_class_init(ObjectClass *klass, void *data)
diff --git a/include/hw/timer/a9gtimer.h b/include/hw/timer/a9gtimer.h
index 3b63d14927..ff9baf1c77 100644
--- a/include/hw/timer/a9gtimer.h
+++ b/include/hw/timer/a9gtimer.h
@@ -77,6 +77,7 @@ struct A9GTimerState {
MemoryRegion iomem;
/* static props */
uint64_t freq_hz;
+ uint64_t periphclk_divider;
uint32_t num_cpu;
QEMUTimer *timer;
diff --git a/include/hw/timer/arm_mptimer.h b/include/hw/timer/arm_mptimer.h
index da43a3d351..061934e4b5 100644
--- a/include/hw/timer/arm_mptimer.h
+++ b/include/hw/timer/arm_mptimer.h
@@ -32,6 +32,7 @@ typedef struct {
uint32_t status;
struct ptimer_state *timer;
uint64_t freq_hz;
+ uint64_t periphclk_divider;
qemu_irq irq;
MemoryRegion iomem;
} TimerBlock;
@@ -45,6 +46,7 @@ struct ARMMPTimerState {
/*< public >*/
uint64_t freq_hz;
+ uint64_t periphclk_divider;
uint32_t num_cpu;
TimerBlock timerblock[ARM_MPTIMER_MAX_CPUS];
MemoryRegion iomem;
--
2.47.3